{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:36:23Z","timestamp":1750307783709,"version":"3.41.0"},"reference-count":17,"publisher":"Association for Computing Machinery (ACM)","issue":"5","license":[{"start":{"date-parts":[[2007,12,1]],"date-time":"2007-12-01T00:00:00Z","timestamp":1196467200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGARCH Comput. Archit. News"],"published-print":{"date-parts":[[2007,12]]},"abstract":"<jats:p>\n            Leakage power loss is a major concern in deep-submicron technologies as it drains the battery even when a circuit is completely idle. In this paper, we first present a novel leakage reduction technique and then compare and contrast it with other well established leakage reduction techniques. Our leakage reduction technique achieves cancellation of leakage effects in both the pull-up network (PUN) as well as the pull-down network (PDN) for CMOS circuits. It involves voltage balancing in the PUN and PDN paths using a combination of high-\n            <jats:italic>V<\/jats:italic>\n            <jats:sub>\n              <jats:italic>T<\/jats:italic>\n            <\/jats:sub>\n            (high voltage threshold) and standard-\n            <jats:italic>V<\/jats:italic>\n            <jats:sub>\n              <jats:italic>T<\/jats:italic>\n            <\/jats:sub>\n            sleep transistors. Experiments conducted on a variety of multi-level combinational MCNC'91 benchmarks show significant savings in leakage power (upto 3 orders of magnitude), with lesser area and delay penalty using our leakage reduction technique when compared to other techniques.\n          <\/jats:p>","DOI":"10.1145\/1360464.1360471","type":"journal-article","created":{"date-parts":[[2008,4,8]],"date-time":"2008-04-08T15:40:00Z","timestamp":1207669200000},"page":"10-16","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":10,"title":["VCLEARIT"],"prefix":"10.1145","volume":"35","author":[{"given":"Preetham","family":"Lakshmikanthan","sequence":"first","affiliation":[{"name":"Syracuse University, Syracuse, NY"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Adrian","family":"Nu\u00f1ez","sequence":"additional","affiliation":[{"name":"Syracuse University, Syracuse, NY"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2007,12]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/7384.928306"},{"key":"e_1_2_1_2_1","doi-asserted-by":"crossref","DOI":"10.1007\/b101914","volume-title":"Power Aware Design Methodologies","author":"Pedram M.","year":"2002","unstructured":"M. Pedram and J. M. Rabaey , Power Aware Design Methodologies . Massachusetts, USA : Kluwer Academic Publishers , 2002 , p. 544. M. Pedram and J. M. Rabaey, Power Aware Design Methodologies. Massachusetts, USA: Kluwer Academic Publishers, 2002, p. 544."},{"key":"e_1_2_1_3_1","volume-title":"Low-Voltage","author":"Yeo K. S.","year":"2005","unstructured":"K. S. Yeo and K. Roy , Low-Voltage , Low-Power VLSI Subsystems. New York, USA : McGraw-Hill , 2005 , p. 293. K. S. Yeo and K. Roy, Low-Voltage, Low-Power VLSI Subsystems. New York, USA: McGraw-Hill, 2005, p. 293."},{"key":"e_1_2_1_4_1","unstructured":"\"International technology roadmap for semiconductors (itrs-06).\" {Online}. Available: http:\/\/www.itrs.net\/Links\/2006Update\/2006UpdateFinal.htm  \"International technology roadmap for semiconductors (itrs-06).\" {Online}. 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Yang \"Logic synthesis and optimization benchmarks user guide version 3.0 \" Microelectronics Center of North Carolina Technical Report January 1991.  S. Yang \"Logic synthesis and optimization benchmarks user guide version 3.0 \" Microelectronics Center of North Carolina Technical Report January 1991."},{"key":"e_1_2_1_17_1","unstructured":"\"Berkeley predictive technology model (bptm).\" http:\/\/www-device.eecs.berkeley.edu\/~ptm.  \"Berkeley predictive technology model (bptm).\" http:\/\/www-device.eecs.berkeley.edu\/~ptm."}],"container-title":["ACM SIGARCH Computer Architecture News"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1360464.1360471","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1360464.1360471","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:56:09Z","timestamp":1750254969000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1360464.1360471"}},"subtitle":["a VLSI CMOS circuit leakage reduction technique for nanoscale technologies"],"short-title":[],"issued":{"date-parts":[[2007,12]]},"references-count":17,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2007,12]]}},"alternative-id":["10.1145\/1360464.1360471"],"URL":"https:\/\/doi.org\/10.1145\/1360464.1360471","relation":{},"ISSN":["0163-5964"],"issn-type":[{"type":"print","value":"0163-5964"}],"subject":[],"published":{"date-parts":[[2007,12]]},"assertion":[{"value":"2007-12-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}