{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:36:23Z","timestamp":1750307783588,"version":"3.41.0"},"reference-count":6,"publisher":"Association for Computing Machinery (ACM)","issue":"5","license":[{"start":{"date-parts":[[2007,12,1]],"date-time":"2007-12-01T00:00:00Z","timestamp":1196467200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGARCH Comput. Archit. News"],"published-print":{"date-parts":[[2007,12]]},"abstract":"<jats:p>To deal with the increasing varitations of the intra-chip transisters, one promising approach is to dynamically detect and recover the timing-errors with microarchitecutre. This will induce dependability and efficiency into microprocessors because it allows VLSI to operate at the optimum frequency and voltage while ensuring accuracy.<\/jats:p>\n          <jats:p>A few approaches for dynamically detecting timing-errors have been proposed, but none of them have focused on register writes. In this paper, we propose a technique for detecting and recovering from timing errors during register writes. We introduce a verifying technique that uses additional buffer (called the write assurance buffer (WAB)) which is provided with a sufficient timing margin. The evaluation results reveal a performance degradation of 4.5% using an 8-entry WAB; this value becomes negligible when a 16-entry WAB is used.<\/jats:p>","DOI":"10.1145\/1360464.1360473","type":"journal-article","created":{"date-parts":[[2008,4,8]],"date-time":"2008-04-08T15:40:00Z","timestamp":1207669200000},"page":"25-31","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Preventing timing errors on register writes"],"prefix":"10.1145","volume":"35","author":[{"given":"Hidetsugu","family":"Irie","sequence":"first","affiliation":[{"name":"Japan Science and Technology Agency, Saitama, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ken","family":"Sugimoto","sequence":"additional","affiliation":[{"name":"The University of Tokyo, Tokyo, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Masahiro","family":"Goshima","sequence":"additional","affiliation":[{"name":"The University of Tokyo, Tokyo, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shuich","family":"Sakai","sequence":"additional","affiliation":[{"name":"The University of Tokyo, Tokyo, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2007,12]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2004.1274005"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/268806.268810"},{"key":"e_1_2_1_3_1","volume-title":"Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. Int. Symp. on Microarchitectre","author":"Ernst D.","year":"2003","unstructured":"D. Ernst , N. Kim , S. Das , S. Pant , T. Pham , R. Rao , C. Ziesler , D. Blaauw , T. Austin , and T. Mudge . Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. Int. Symp. on Microarchitectre , 2003 . D. Ernst, N. Kim, S. Das, S. Pant, T. Pham, R. Rao, C. Ziesler, D. Blaauw, T. Austin, and T. Mudge. Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. Int. Symp. on Microarchitectre, 2003."},{"key":"e_1_2_1_4_1","volume-title":"Timing Error Correction Techniques for Voltage-scalable On-chip Memories. IEEE Int. Symp. on Circuits and Systems, 4: 3563--3566","author":"Karl E.","year":"2005","unstructured":"E. Karl , D. Sylvester , and D. Blaauw . Timing Error Correction Techniques for Voltage-scalable On-chip Memories. IEEE Int. Symp. on Circuits and Systems, 4: 3563--3566 , 2005 . E. Karl, D. Sylvester, and D. Blaauw. Timing Error Correction Techniques for Voltage-scalable On-chip Memories. IEEE Int. Symp. on Circuits and Systems, 4:3563--3566, 2005."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.852295"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859620"}],"container-title":["ACM SIGARCH Computer Architecture News"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1360464.1360473","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1360464.1360473","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:56:09Z","timestamp":1750254969000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1360464.1360473"}},"subtitle":["mechanisms of detections and recoveries"],"short-title":[],"issued":{"date-parts":[[2007,12]]},"references-count":6,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2007,12]]}},"alternative-id":["10.1145\/1360464.1360473"],"URL":"https:\/\/doi.org\/10.1145\/1360464.1360473","relation":{},"ISSN":["0163-5964"],"issn-type":[{"type":"print","value":"0163-5964"}],"subject":[],"published":{"date-parts":[[2007,12]]},"assertion":[{"value":"2007-12-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}