{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:36:23Z","timestamp":1750307783242,"version":"3.41.0"},"reference-count":11,"publisher":"Association for Computing Machinery (ACM)","issue":"5","license":[{"start":{"date-parts":[[2007,12,1]],"date-time":"2007-12-01T00:00:00Z","timestamp":1196467200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGARCH Comput. Archit. News"],"published-print":{"date-parts":[[2007,12]]},"abstract":"<jats:p>\n            Recent embedded systems have switched to fully programmable parallel architectures. To make sure all corner cases usually present in real applications are supported and efficiently implemented in this switch of implementation, new solutions must be found. We introduce the\n            <jats:italic>integral parallel architecture<\/jats:italic>\n            (IPA) as a solution supporting intensive data computation in System-on-a-chip (Soc) implementations, fitting in a\n            <jats:italic>small area<\/jats:italic>\n            , and requiring\n            <jats:italic>low power<\/jats:italic>\n            . An IPA supports naturally all three possible styles of parallelism:\n            <jats:italic>data, time<\/jats:italic>\n            , and\n            <jats:italic>speculative<\/jats:italic>\n            .\n          <\/jats:p>\n          <jats:p>\n            As an illustrative example, we present the\n            <jats:bold>\n              <jats:italic>BA1024<\/jats:italic>\n            <\/jats:bold>\n            chip, a fully programmable SoC designed by\n            <jats:italic>BrightScale, Inc.<\/jats:italic>\n            for HDTV codecs. Its main performance figures include 60\n            <jats:italic>GOPS\/Watt<\/jats:italic>\n            and 2\n            <jats:italic>GOPS\/mm<\/jats:italic>\n            <jats:sup>2<\/jats:sup>\n            , representing an efficient IPA approach for embedded computation.\n          <\/jats:p>","DOI":"10.1145\/1360464.1360474","type":"journal-article","created":{"date-parts":[[2008,4,8]],"date-time":"2008-04-08T15:40:00Z","timestamp":1207669200000},"page":"32-38","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":16,"title":["Not multi-, but many-core"],"prefix":"10.1145","volume":"35","author":[{"given":"Mihaela","family":"Mali\u0163a","sequence":"first","affiliation":[{"name":"St. Anselm College, Manchester, NH"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gheorghe","family":"\u015etefan","sequence":"additional","affiliation":[{"name":"BrightScale Inc., Sunnyvale, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dominique","family":"Thi\u00e9baut","sequence":"additional","affiliation":[{"name":"Smith College, Northampton, MA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2007,12]]},"reference":[{"volume-title":"Berkeley","year":"2006","author":"Asanovic K.","key":"e_1_2_1_1_1"},{"unstructured":"V. Borkar. Platform 2015: Intel processor and platform evolution for the next decade. Intel Corporation white paper 2005.  V. Borkar. Platform 2015: Intel processor and platform evolution for the next decade. Intel Corporation white paper 2005.","key":"e_1_2_1_2_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_3_1","DOI":"10.1109\/TC.1972.5009071"},{"key":"e_1_2_1_4_1","first-page":"2","article-title":"General recursive functions of natural numbers","author":"Kleene S. C.","year":"1937","journal-title":"Journal of Symbolic Logic"},{"doi-asserted-by":"publisher","key":"e_1_2_1_5_1","DOI":"10.1109\/ICCGI.2006.65"},{"unstructured":"B. Mitu. private communication 2005.  B. Mitu. private communication 2005.","key":"e_1_2_1_6_1"},{"volume-title":"SPRING PROCESSOR FORUM: Power-Efficient Design","year":"2006","author":"Stefan G.","key":"e_1_2_1_7_1"},{"volume-title":"4th International System-on-Chip (SoC) Conference and Exhibit. SOC Conference","year":"2006","author":"Stefan G.","key":"e_1_2_1_8_1"},{"volume-title":"Hot Chips: A Symposium on High Performance Chips. Stanford U.","year":"2006","author":"Stefan G.","key":"e_1_2_1_9_1"},{"volume-title":"BARC","year":"2007","author":"Thiebaut D.","key":"e_1_2_1_10_1"},{"volume-title":"ICCGI 2006","year":"2006","author":"Thiebaut D.","key":"e_1_2_1_11_1"}],"container-title":["ACM SIGARCH Computer Architecture News"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1360464.1360474","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1360464.1360474","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:56:09Z","timestamp":1750254969000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1360464.1360474"}},"subtitle":["designing integral parallel architectures for embedded computation"],"short-title":[],"issued":{"date-parts":[[2007,12]]},"references-count":11,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2007,12]]}},"alternative-id":["10.1145\/1360464.1360474"],"URL":"https:\/\/doi.org\/10.1145\/1360464.1360474","relation":{},"ISSN":["0163-5964"],"issn-type":[{"type":"print","value":"0163-5964"}],"subject":[],"published":{"date-parts":[[2007,12]]},"assertion":[{"value":"2007-12-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}