{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,9]],"date-time":"2026-01-09T00:32:40Z","timestamp":1767918760224,"version":"3.49.0"},"publisher-location":"New York, NY, USA","reference-count":17,"publisher":"ACM","license":[{"start":{"date-parts":[[2008,3,16]],"date-time":"2008-03-16T00:00:00Z","timestamp":1205625600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2008,3,16]]},"DOI":"10.1145\/1363686.1364037","type":"proceedings-article","created":{"date-parts":[[2008,4,29]],"date-time":"2008-04-29T13:04:11Z","timestamp":1209474251000},"page":"1492-1497","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":12,"title":["VHDL vs. Bluespec system verilog"],"prefix":"10.1145","author":[{"given":"Flavius","family":"Gruian","sequence":"first","affiliation":[{"name":"Lund University, Lund, Sweden"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mark","family":"Westmijze","sequence":"additional","affiliation":[{"name":"University of Twente, Enschede, The Netherlands"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2008,3,16]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"IEEE","author":"Language Reference Manual VHDL","year":"1994","unstructured":"IEEE, Standard VHDL Language Reference Manual : IEEE Std 1076--1993 . IEEE , August 1994 . IEEE, Standard VHDL Language Reference Manual: IEEE Std 1076--1993. IEEE, August 1994."},{"key":"e_1_3_2_1_2_1","unstructured":"Bluespec Inc. http:\/\/www.bluespec.com 2007.  Bluespec Inc. http:\/\/www.bluespec.com 2007."},{"key":"e_1_3_2_1_3_1","volume-title":"MIT","author":"Dave N.","year":"2005","unstructured":"N. Dave . Designing a processor in Bluespec. Master's thesis , MIT , Cambridge, MA , January 2005 . N. Dave. Designing a processor in Bluespec. Master's thesis, MIT, Cambridge, MA, January 2005."},{"key":"e_1_3_2_1_4_1","first-page":"59","volume-title":"International Conference on Formal Methods and Models for Codesign (MEMOCODE '06)","author":"Dave N.","year":"2006","unstructured":"N. Dave , M. Pellauer , S. Gerding , and Arvind. 802.11a transmitter : A case study in microarchitectural exploration . In International Conference on Formal Methods and Models for Codesign (MEMOCODE '06) , pages 59 -- 68 , July 2006 . N. Dave, M. Pellauer, S. Gerding, and Arvind. 802.11a transmitter: A case study in microarchitectural exploration. In International Conference on Formal Methods and Models for Codesign (MEMOCODE '06), pages 59--68, July 2006."},{"key":"e_1_3_2_1_5_1","volume-title":"System Design - A Practical Guide with SpecC","author":"Gerstlauer A.","year":"2001","unstructured":"A. Gerstlauer , R. Domer , J. Peng , and D. D. Gajski . System Design - A Practical Guide with SpecC . Kluwer academic, 2001 . A. Gerstlauer, R. Domer, J. Peng, and D. D. Gajski. System Design - A Practical Guide with SpecC. Kluwer academic, 2001."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1066677.1066877"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1007\/11572961_23"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/SYNASC.2007.12"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1288940.1288973"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.5555\/647030.714800"},{"key":"e_1_3_2_1_11_1","volume-title":"Workshop on Java Technologies for Real-Time and Embedded Systems","author":"Schoeberl M.","year":"2003","unstructured":"M. Schoeberl . JOP : A Java optimized processor . In Workshop on Java Technologies for Real-Time and Embedded Systems , November 2003 . M. Schoeberl. JOP: A Java optimized processor. In Workshop on Java Technologies for Real-Time and Embedded Systems, November 2003."},{"key":"e_1_3_2_1_12_1","series-title":"LNCS","doi-asserted-by":"crossref","first-page":"371","DOI":"10.1007\/978-3-540-30470-8_52","volume-title":"On the Move to Meaningful Internet Systems 2004: Workshop on Java Technologies for Real-Time and Embedded Systems (JTRES","author":"Schoeberl M.","year":"2004","unstructured":"M. Schoeberl . A time predictable instruction cache for a Java processor . In On the Move to Meaningful Internet Systems 2004: Workshop on Java Technologies for Real-Time and Embedded Systems (JTRES 2004 ), volume 3292 of LNCS , pages 371 -- 382 , Agia Napa, Cyprus, October 2004. Springer . M. Schoeberl. A time predictable instruction cache for a Java processor. In On the Move to Meaningful Internet Systems 2004: Workshop on Java Technologies for Real-Time and Embedded Systems (JTRES 2004), volume 3292 of LNCS, pages 371--382, Agia Napa, Cyprus, October 2004. Springer."},{"key":"e_1_3_2_1_14_1","unstructured":"SystemC. the open systemC initiative. http:\/\/www.systemc.org.  SystemC. the open systemC initiative. http:\/\/www.systemc.org."},{"key":"e_1_3_2_1_15_1","volume-title":"The Verilog Hardware Description Language","author":"Thomas D. E.","year":"2002","unstructured":"D. E. Thomas and P. R. Moorby . The Verilog Hardware Description Language . Springer , 5 edition, June 2002 . D. E. Thomas and P. R. Moorby. The Verilog Hardware Description Language. Springer, 5 edition, June 2002."},{"key":"e_1_3_2_1_16_1","volume-title":"International Conference on Computer Design","author":"Wunderlich R. E.","year":"2004","unstructured":"R. E. Wunderlich and J. C. Hoe . In-system FPGA prototyping of an Itanium microarchitecture . In International Conference on Computer Design , October 2004 . R. E. Wunderlich and J. C. Hoe. In-system FPGA prototyping of an Itanium microarchitecture. In International Conference on Computer Design, October 2004."},{"key":"e_1_3_2_1_17_1","volume-title":"January","year":"2007","unstructured":"Xilinx. ChipScope Pro Software and Cores User Guide, v9.1.01 edition , January 2007 . Xilinx. ChipScope Pro Software and Cores User Guide, v9.1.01 edition, January 2007."},{"key":"e_1_3_2_1_18_1","unstructured":"Xilinx Inc. Http:\/\/www.xilinx.com\/ 2007.  Xilinx Inc. Http:\/\/www.xilinx.com\/ 2007."}],"event":{"name":"SAC '08: The 2008 ACM Symposium on Applied Computing","location":"Fortaleza, Ceara Brazil","acronym":"SAC '08","sponsor":["SIGAPP ACM Special Interest Group on Applied Computing"]},"container-title":["Proceedings of the 2008 ACM symposium on Applied computing"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1363686.1364037","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1363686.1364037","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:38:56Z","timestamp":1750253936000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1363686.1364037"}},"subtitle":["a case study on a Java embedded architecture"],"short-title":[],"issued":{"date-parts":[[2008,3,16]]},"references-count":17,"alternative-id":["10.1145\/1363686.1364037","10.1145\/1363686"],"URL":"https:\/\/doi.org\/10.1145\/1363686.1364037","relation":{},"subject":[],"published":{"date-parts":[[2008,3,16]]},"assertion":[{"value":"2008-03-16","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}