{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:36:54Z","timestamp":1750307814470,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":12,"publisher":"ACM","license":[{"start":{"date-parts":[[2008,5,4]],"date-time":"2008-05-04T00:00:00Z","timestamp":1209859200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2008,5,4]]},"DOI":"10.1145\/1366110.1366162","type":"proceedings-article","created":{"date-parts":[[2008,5,6]],"date-time":"2008-05-06T14:37:21Z","timestamp":1210084641000},"page":"213-218","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Pipelined network of PLA based circuit design"],"prefix":"10.1145","author":[{"given":"Suganth","family":"Paul","sequence":"first","affiliation":[{"name":"Intel Corporation, Austin, TX, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rajesh","family":"Garg","sequence":"additional","affiliation":[{"name":"Texas A&amp;M University, College Station, TX, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sunil P.","family":"Khatri","sequence":"additional","affiliation":[{"name":"Texas A&amp;M University, College Station, TX, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2008,5,4]]},"reference":[{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.5555\/602902.602995"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382645"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.811454"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/513918.513970"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/774572.774652"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147021"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2005.75"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1127908.1127960"},{"key":"e_1_3_2_1_10_1","volume-title":"Digital Integrated Circuits: A Design Perspective","author":"Rabaey J.","year":"1996","unstructured":"J. Rabaey , Digital Integrated Circuits: A Design Perspective . Prentice Hall Electronics and VLSI Series , Prentice Hall , 1996 . J. Rabaey, Digital Integrated Circuits: A Design Perspective. Prentice Hall Electronics and VLSI Series, Prentice Hall, 1996."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.5555\/577427"},{"key":"e_1_3_2_1_13_1","volume-title":"Berkeley UCB\/ERL Memo M520","author":"Nagel L.","year":"1995","unstructured":"L. Nagel , \"Spice : A computer program to simulate computer circuits,\" in University of California , Berkeley UCB\/ERL Memo M520 , May 1995 . L. Nagel, \"Spice: A computer program to simulate computer circuits,\" in University of California, Berkeley UCB\/ERL Memo M520, May 1995."},{"key":"e_1_3_2_1_14_1","first-page":"201","author":"Cao Y.","year":"2000","unstructured":"Y. Cao , T. Sato , D. Sylvester , M. Orshansky , and C. Hu , \"New paradigm of predictive MOSFET and interconnect modeling for early circuit design,\" in Proc. of IEEE Custom Integrated Circuit Conference , pp. 201 -- 204 , Jun 2000 . http:\/\/www-device.eecs.berkeley.edu\/ptm. Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu, \"New paradigm of predictive MOSFET and interconnect modeling for early circuit design,\" in Proc. of IEEE Custom Integrated Circuit Conference, pp. 201--204, Jun 2000. http:\/\/www-device.eecs.berkeley.edu\/ptm.","journal-title":"of IEEE Custom Integrated Circuit Conference"}],"event":{"name":"GLSVLSI08: Great Lakes Symposium on VLSI 2008","sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"],"location":"Orlando Florida USA","acronym":"GLSVLSI08"},"container-title":["Proceedings of the 18th ACM Great Lakes symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1366110.1366162","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1366110.1366162","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:57:40Z","timestamp":1750255060000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1366110.1366162"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,5,4]]},"references-count":12,"alternative-id":["10.1145\/1366110.1366162","10.1145\/1366110"],"URL":"https:\/\/doi.org\/10.1145\/1366110.1366162","relation":{},"subject":[],"published":{"date-parts":[[2008,5,4]]},"assertion":[{"value":"2008-05-04","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}