{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:36:54Z","timestamp":1750307814462,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":17,"publisher":"ACM","license":[{"start":{"date-parts":[[2008,5,4]],"date-time":"2008-05-04T00:00:00Z","timestamp":1209859200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2008,5,4]]},"DOI":"10.1145\/1366110.1366176","type":"proceedings-article","created":{"date-parts":[[2008,5,6]],"date-time":"2008-05-06T14:37:21Z","timestamp":1210084641000},"page":"273-278","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":16,"title":["A linear programming formulation for security-aware gate sizing"],"prefix":"10.1145","author":[{"given":"Koustav","family":"Bhattacharya","sequence":"first","affiliation":[{"name":"University of South Florida, Tampa, FL, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nagarajan","family":"Ranganathan","sequence":"additional","affiliation":[{"name":"University of South Florida, Tampa, FL, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2008,5,4]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.5555\/949970.950019"},{"key":"e_1_3_2_1_2_1","first-page":"326","volume-title":"Proc. of ICCAD","author":"Fishburn J.","year":"1985","unstructured":"J. Fishburn and A. Dunlop . Tilos: A posynomial programming approach to transistor sizing . Proc. of ICCAD , pages 326 -- 328 , 1985 . J. Fishburn and A. Dunlop. Tilos: A posynomial programming approach to transistor sizing. Proc. of ICCAD, pages 326--328, 1985."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2006.131"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.5555\/646764.703989"},{"key":"e_1_3_2_1_5_1","first-page":"9","volume-title":"Workshop on Smartcard Technology","author":"Kommerling O.","year":"1999","unstructured":"O. Kommerling and M. Kuhn . Design principles for tamper-resistant smartcard processors . Workshop on Smartcard Technology , pages 9 -- 20 , 1999 . O. Kommerling and M. Kuhn. Design principles for tamper-resistant smartcard processors. Workshop on Smartcard Technology, pages 9--20, 1999."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1165573.1165614"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.5555\/1032648.1033372"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.5555\/962758.963409"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1015047.1015049"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.248073"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065662"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382535"},{"key":"e_1_3_2_1_13_1","volume-title":"Proc. of Conf. of Solid--State Circuits","author":"Tiri K.","year":"2002","unstructured":"K. Tiri and I. Verbauwhede . A dynamic and differential cmos logic with signal independent power consumption to withstand differential power analysis on smart cards . Proc. of Conf. of Solid--State Circuits , 2002 . K. Tiri and I. Verbauwhede. A dynamic and differential cmos logic with signal independent power consumption to withstand differential power analysis on smart cards. Proc. of Conf. of Solid--State Circuits, 2002."},{"key":"e_1_3_2_1_14_1","first-page":"246","volume-title":"Proc. of DATE","author":"Tiri K.","year":"2004","unstructured":"K. Tiri and I. Verbauwhede . A logic level design methology for a secure dpa resistant asic or fpga implementation . Proc. of DATE , pages 246 -- 251 , 2004 . K. Tiri and I. Verbauwhede. A logic level design methology for a secure dpa resistant asic or fpga implementation. Proc. of DATE, pages 246--251, 2004."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.855939"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2007.48"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.853696"}],"event":{"name":"GLSVLSI08: Great Lakes Symposium on VLSI 2008","sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"],"location":"Orlando Florida USA","acronym":"GLSVLSI08"},"container-title":["Proceedings of the 18th ACM Great Lakes symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1366110.1366176","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1366110.1366176","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:57:40Z","timestamp":1750255060000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1366110.1366176"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,5,4]]},"references-count":17,"alternative-id":["10.1145\/1366110.1366176","10.1145\/1366110"],"URL":"https:\/\/doi.org\/10.1145\/1366110.1366176","relation":{},"subject":[],"published":{"date-parts":[[2008,5,4]]},"assertion":[{"value":"2008-05-04","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}