{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:36:54Z","timestamp":1750307814958,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":18,"publisher":"ACM","license":[{"start":{"date-parts":[[2008,5,4]],"date-time":"2008-05-04T00:00:00Z","timestamp":1209859200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2008,5,4]]},"DOI":"10.1145\/1366110.1366178","type":"proceedings-article","created":{"date-parts":[[2008,5,6]],"date-time":"2008-05-06T14:37:21Z","timestamp":1210084641000},"page":"279-284","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["On efficient generation of instruction sequences to test for delay defects in a processor"],"prefix":"10.1145","author":[{"given":"Sankar","family":"Gurumurthy","sequence":"first","affiliation":[{"name":"University of Texas, Austin, TX, USA"}]},{"given":"Ramtilak","family":"Vemu","sequence":"additional","affiliation":[{"name":"University of Texas, Austin, TX, USA"}]},{"given":"Jacob A.","family":"Abraham","sequence":"additional","affiliation":[{"name":"University of Texas, Austin, TX, USA"}]},{"given":"Suriyaprakash","family":"Natarajan","sequence":"additional","affiliation":[{"name":"Intel Corporation, Santa Clara, CA, USA"}]}],"member":"320","published-online":{"date-parts":[[2008,5,4]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/54.825672"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775920"},{"key":"e_1_3_2_1_3_1","volume-title":"Proceedings of the 18th IEEE VLSI Test Symposium (VTS'00)","author":"Lai W.--C.","year":"2000","unstructured":"W.--C. Lai , A. Krstic , and K.--T. Cheng , \"On testing the path delay faults of a microprocessor using its instruction set,\" in VTS '00 : Proceedings of the 18th IEEE VLSI Test Symposium (VTS'00) , 2000 , p. 15. W.--C. Lai, A. Krstic, and K.--T. Cheng, \"On testing the path delay faults of a microprocessor using its instruction set,\" in VTS '00: Proceedings of the 18th IEEE VLSI Test Symposium (VTS'00), 2000, p. 15."},{"key":"e_1_3_2_1_4_1","first-page":"990","article-title":"Native mode functional test generation for processors with applications to self test and design validation","author":"Shen J.","year":"1998","unstructured":"J. Shen and J. A. Abraham , \" Native mode functional test generation for processors with applications to self test and design validation ,\" in Proceedings of the International Test Conference , Oct 1998 , pp. 990 -- 999 . J. Shen and J. A. Abraham, \"Native mode functional test generation for processors with applications to self test and design validation,\" in Proceedings of the International Test Conference, Oct 1998, pp.990--999.","journal-title":"Proceedings of the International Test Conference"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.5555\/839297.843940"},{"key":"e_1_3_2_1_6_1","first-page":"12","article-title":"Automated mapping of precomputed module--level test sequences to processor instructions","author":"Gurumurthy S.","year":"2005","unstructured":"S. Gurumurthy , S. Vasudevan , and J. A. Abraham , \" Automated mapping of precomputed module--level test sequences to processor instructions ,\" in Proceedings of the International Test Conference , Nov 2005 , p. 12 .3. S. Gurumurthy, S. Vasudevan, and J. A. Abraham, \"Automated mapping of precomputed module--level test sequences to processor instructions,\" in Proceedings of the International Test Conference, Nov 2005, p. 12.3.","journal-title":"Proceedings of the International Test Conference"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2007.13"},{"key":"e_1_3_2_1_8_1","first-page":"592","article-title":"Effective software self--test methodology for processor cores,\" in Proceedings of the conference on Design, automation and test","author":"Kranitis N.","year":"2002","unstructured":"N. Kranitis , A. Paschalis , D. Gizopoulos , and Y. Zorian , \" Effective software self--test methodology for processor cores,\" in Proceedings of the conference on Design, automation and test in Europe , 2002 , pp. 592 -- 597 . N. Kranitis, A. Paschalis, D. Gizopoulos, and Y. Zorian, \"Effective software self--test methodology for processor cores,\" in Proceedings of the conference on Design, automation and test in Europe, 2002, pp. 592--597.","journal-title":"Europe"},{"key":"e_1_3_2_1_9_1","first-page":"1006","volume-title":"Automation and Test in Europe","author":"Corno F.","year":"2003","unstructured":"F. Corno , G. Cumani , M. S. Reorda , and G. Squillero , \" Fully automatic test program generation for microprocessor cores,\" in Proceedings of the conference on Design , Automation and Test in Europe , 2003 , pp. 1006 -- 1011 . F. Corno, G. Cumani, M. S. Reorda, and G. Squillero, \"Fully automatic test program generation for microprocessor cores,\" in Proceedings of the conference on Design, Automation and Test in Europe, 2003, pp. 1006-- 1011."},{"key":"e_1_3_2_1_10_1","first-page":"1080","article-title":"Test program synthesis for path delay faults in microprocessor cores","author":"Lai W.--C.","year":"2000","unstructured":"W.--C. Lai , A. Krstic , and K.-T. Cheng , \" Test program synthesis for path delay faults in microprocessor cores ,\" in Proceedings of the International Test Conference , 2000 , p. 1080 . W.--C. Lai, A. Krstic, and K.-T. Cheng, \"Test program synthesis for path delay faults in microprocessor cores,\" in Proceedings of the International Test Conference, 2000, p. 1080.","journal-title":"Proceedings of the International Test Conference"},{"key":"e_1_3_2_1_11_1","first-page":"5686","article-title":"Instruction--based delay fault self--testing of pipelined processor cores","author":"Singh V.","year":"2005","unstructured":"V. Singh , M. Inoue , K. K. Saluja , and H. Fujiwara , \" Instruction--based delay fault self--testing of pipelined processor cores ,\" in IEEE International Symposium on Circuits and Systems , 2005 , pp. 5686 -- 5689 . V. Singh, M. Inoue, K. K. Saluja, and H. Fujiwara, \"Instruction--based delay fault self--testing of pipelined processor cores,\" in IEEE International Symposium on Circuits and Systems, 2005, pp. 5686--5689.","journal-title":"IEEE International Symposium on Circuits and Systems"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2007.13"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2005.38"},{"key":"e_1_3_2_1_14_1","unstructured":"\"BMC engine of Symbolic Model Verifier \" http:\/\/www--cad.eecs.berkeley.edu\/~kenmcmil\/smv\/.  \"BMC engine of Symbolic Model Verifier \" http:\/\/www--cad.eecs.berkeley.edu\/~kenmcmil\/smv\/."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1023\/A:1012259227622"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1228784.1228881"},{"key":"e_1_3_2_1_17_1","volume-title":"The University of Texas","author":"Jayabharathi R.","year":"1999","unstructured":"R. Jayabharathi , \"Hierarchical timing verification and delay fault testing,\" PhD Dissertation , The University of Texas , Aug. 1999 . R. Jayabharathi, \"Hierarchical timing verification and delay fault testing,\" PhD Dissertation, The University of Texas, Aug. 1999."},{"key":"e_1_3_2_1_18_1","unstructured":"\"OR1200 RISC processor \" http:\/\/www.opencores.org.  \"OR1200 RISC processor \" http:\/\/www.opencores.org."}],"event":{"name":"GLSVLSI08: Great Lakes Symposium on VLSI 2008","sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"],"location":"Orlando Florida USA","acronym":"GLSVLSI08"},"container-title":["Proceedings of the 18th ACM Great Lakes symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1366110.1366178","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1366110.1366178","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:57:40Z","timestamp":1750255060000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1366110.1366178"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,5,4]]},"references-count":18,"alternative-id":["10.1145\/1366110.1366178","10.1145\/1366110"],"URL":"https:\/\/doi.org\/10.1145\/1366110.1366178","relation":{},"subject":[],"published":{"date-parts":[[2008,5,4]]},"assertion":[{"value":"2008-05-04","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}