{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:36:38Z","timestamp":1750307798535,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":19,"publisher":"ACM","license":[{"start":{"date-parts":[[2008,5,4]],"date-time":"2008-05-04T00:00:00Z","timestamp":1209859200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2008,5,4]]},"DOI":"10.1145\/1366110.1366209","type":"proceedings-article","created":{"date-parts":[[2008,5,6]],"date-time":"2008-05-06T14:37:21Z","timestamp":1210084641000},"page":"411-416","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["FEKIS"],"prefix":"10.1145","author":[{"given":"Pu","family":"Liu","sequence":"first","affiliation":[{"name":"University of California, Riverside, Riverside, CA, USA"}]},{"given":"Sheldon X.-D.","family":"Tan","sequence":"additional","affiliation":[{"name":"University of California, Riverside, Riverside, CA, USA"}]},{"given":"Wei","family":"Wu","sequence":"additional","affiliation":[{"name":"Intel Corporation, Santa Clara, CA, USA"}]},{"given":"Murli","family":"Tirumala","sequence":"additional","affiliation":[{"name":"Intel Corporation, Santa Clara, CA, USA"}]}],"member":"320","published-online":{"date-parts":[[2008,5,4]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"http:\/\/www.spec.org\/cpu2000\/CFP2000\/.  http:\/\/www.spec.org\/cpu2000\/CFP2000\/."},{"key":"e_1_3_2_1_2_1","unstructured":"International technology roadmap for semiconductors(itrs) 2004update 2004. http:\/\/public.itrs.net.  International technology roadmap for semiconductors(itrs) 2004update 2004. http:\/\/public.itrs.net."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.5555\/580550.876439"},{"key":"e_1_3_2_1_4_1","volume-title":"Intel Technology Journal, First Quarter","author":"Gunther S.","year":"2001","unstructured":"S. Gunther , F. Binns , D. Carmean , and J. Hall . Managing the impact of increasing microprocessor power consumption . In Intel Technology Journal, First Quarter 2001 . S. Gunther, F. Binns, D. Carmean, and J. Hall. Managing the impact of increasing microprocessor power consumption. In Intel Technology Journal, First Quarter 2001."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996572"},{"key":"e_1_3_2_1_6_1","article-title":"Thermal modeling for cmos vlsi systems","author":"Huang W.","unstructured":"W. Huang , S. Ghosh , K. Sankaranarayanan , K. Skadron , and M. R. Stan . Hotspot : Thermal modeling for cmos vlsi systems . IEEE Transactions on Component Packaging and Manufacturing Technology, to appear. W. Huang, S. Ghosh, K. Sankaranarayanan, K. Skadron, and M. R.Stan. Hotspot: Thermal modeling for cmos vlsi systems. IEEE Transactions on Component Packaging and Manufacturing Technology, to appear.","journal-title":"IEEE Transactions on Component Packaging and Manufacturing Technology, to appear."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996800"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2005.448"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2005.46"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2006.88"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.873898"},{"key":"e_1_3_2_1_12_1","unstructured":"K. Sankaranarayanan S. Velusamy M. R. Stan and K. Skadron. A case for thermal-aware floorplanning at the microarchitectural level. The Journal of Instruction-Level Parallelism to appear.  K. Sankaranarayanan S. Velusamy M. R. Stan and K. Skadron. A case for thermal-aware floorplanning at the microarchitectural level. The Journal of Instruction-Level Parallelism to appear."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.5555\/645988.674158"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859620"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.5555\/1199445"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337407"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1255456.1255462"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1243\/PIME_PROC_1994_208_148_02"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1016\/0045-7825(95)00876-4"}],"event":{"name":"GLSVLSI08: Great Lakes Symposium on VLSI 2008","sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"],"location":"Orlando Florida USA","acronym":"GLSVLSI08"},"container-title":["Proceedings of the 18th ACM Great Lakes symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1366110.1366209","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1366110.1366209","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:56:29Z","timestamp":1750254989000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1366110.1366209"}},"subtitle":["a fast architecture-level thermal analyzer for online thermal regulation"],"short-title":[],"issued":{"date-parts":[[2008,5,4]]},"references-count":19,"alternative-id":["10.1145\/1366110.1366209","10.1145\/1366110"],"URL":"https:\/\/doi.org\/10.1145\/1366110.1366209","relation":{},"subject":[],"published":{"date-parts":[[2008,5,4]]},"assertion":[{"value":"2008-05-04","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}