{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:36:39Z","timestamp":1750307799396,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":9,"publisher":"ACM","license":[{"start":{"date-parts":[[2008,5,4]],"date-time":"2008-05-04T00:00:00Z","timestamp":1209859200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2008,5,4]]},"DOI":"10.1145\/1366110.1366215","type":"proceedings-article","created":{"date-parts":[[2008,5,6]],"date-time":"2008-05-06T14:37:21Z","timestamp":1210084641000},"page":"441-444","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["12bits 40mhz pipelined ADC with duty-correction circuit"],"prefix":"10.1145","author":[{"given":"Jaeyong","family":"Lee","sequence":"first","affiliation":[{"name":"Inha University, Incheon, South Korea"}]},{"given":"Sungil","family":"Cho","sequence":"additional","affiliation":[{"name":"Inha University, Incheon, South Korea"}]},{"given":"Kwangsub","family":"Yoon","sequence":"additional","affiliation":[{"name":"Inha University, Incheon, South Korea"}]}],"member":"320","published-online":{"date-parts":[[2008,5,4]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1049\/el:20020657"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.820882"},{"key":"e_1_3_2_1_3_1","first-page":"954","article-title":"A pipeline 5Msample\/s 9bit analog-to-digital converter","volume":"22","author":"Gray S.H.","year":"1987","unstructured":"Lewis, S.H. and Gray , P.R ., \" A pipeline 5Msample\/s 9bit analog-to-digital converter ,\" IEEE JSSC , vol. SC-22 , pp. 954 -- 961 , Dec. 1987 . Lewis, S.H. and Gray, P.R., \"A pipeline 5Msample\/s 9bit analog-to-digital converter,\" IEEE JSSC, vol. SC-22, pp.954--61, Dec. 1987.","journal-title":"IEEE JSSC"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.62176"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.845972"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.568836"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1996.542317"},{"key":"e_1_3_2_1_8_1","first-page":"4","article-title":"An All--Digital CMOS Duty Cycle Correction Circuit with a duty cycle correction range of 15-to-85% for multi-phase applications","volume":"88","author":"Jang J.N.","year":"2005","unstructured":"J.N. Jang and H.J. Park , \" An All--Digital CMOS Duty Cycle Correction Circuit with a duty cycle correction range of 15-to-85% for multi-phase applications ,\" IEICE TRANS. Electron. , Vol. E88 -C, NO. 4 , pp.773-7, Apr. 2005 . J.N. Jang and H.J. Park, \"An All--Digital CMOS Duty Cycle Correction Circuit with a duty cycle correction range of 15-to-85% for multi-phase applications,\" IEICE TRANS. Electron., Vol.E88-C, NO.4, pp.773-7, Apr. 2005.","journal-title":"IEICE TRANS. Electron."},{"key":"e_1_3_2_1_9_1","first-page":"5","article-title":"A 10b 100MS\/s 1.4mm2 56mW 0.18um CMOS A\/D Converter with 3-D Fully Symmetrical Capacitors","volume":"89","author":"Min B.","year":"2006","unstructured":"B. Min , Y. Cho , H. Chae , H. Park and S. Lee , \" A 10b 100MS\/s 1.4mm2 56mW 0.18um CMOS A\/D Converter with 3-D Fully Symmetrical Capacitors ,\" IEICE Trans. on Electronics , vol. E89 -C, no. 5 , pp. 630--635, May 2006 . B. Min, Y. Cho, H. Chae, H. Park and S. Lee, \"A 10b 100MS\/s 1.4mm2 56mW 0.18um CMOS A\/D Converter with 3-D Fully Symmetrical Capacitors,\" IEICE Trans. on Electronics, vol. E89-C, no. 5, pp. 630--635, May 2006.","journal-title":"IEICE Trans. on Electronics"}],"event":{"name":"GLSVLSI08: Great Lakes Symposium on VLSI 2008","sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"],"location":"Orlando Florida USA","acronym":"GLSVLSI08"},"container-title":["Proceedings of the 18th ACM Great Lakes symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1366110.1366215","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1366110.1366215","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:56:30Z","timestamp":1750254990000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1366110.1366215"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,5,4]]},"references-count":9,"alternative-id":["10.1145\/1366110.1366215","10.1145\/1366110"],"URL":"https:\/\/doi.org\/10.1145\/1366110.1366215","relation":{},"subject":[],"published":{"date-parts":[[2008,5,4]]},"assertion":[{"value":"2008-05-04","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}