{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:36:40Z","timestamp":1750307800013,"version":"3.41.0"},"reference-count":35,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2008,7,1]],"date-time":"2008-07-01T00:00:00Z","timestamp":1214870400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CCR-0204077"],"award-info":[{"award-number":["CCR-0204077"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2008,7]]},"abstract":"<jats:p>Many system-on-chip (SoC) integrated circuits contain embedded cores with different scan frequencies. To better meet the test requirements for such heterogeneous SoCs, leading tester companies have recently introduced port-scalable testers, which can simultaneously drive groups of channels at different data rates. However, the number of tester channels available for scan testing is limited; therefore, a higher shift frequency can increase the test time for a core if the resulting test access architecture reduces the bit-width used to access it. We present a scalable test planning technique that exploits port scalability of testers to reduce SoC test time. We compare the proposed heuristic optimization method to two baseline methods based on prior works that use a single scan data rate for all embedded cores. We also propose a power-aware test planning technique to effectively utilize port-scalable testers under constraints of test power consumption. Experimental results are presented for power-aware test scheduling to illustrate the impact of power constraints on overall test time.<\/jats:p>","DOI":"10.1145\/1367045.1367062","type":"journal-article","created":{"date-parts":[[2008,7,29]],"date-time":"2008-07-29T13:22:19Z","timestamp":1217337739000},"page":"1-19","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["Power-aware SoC test planning for effective utilization of port-scalable testers"],"prefix":"10.1145","volume":"13","author":[{"given":"Anuja","family":"Sehgal","sequence":"first","affiliation":[{"name":"Duke University, Durham, NC"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sudarshan","family":"Bahukudumbi","sequence":"additional","affiliation":[{"name":"Duke University, Durham, NC"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Krishnendu","family":"Chakrabarty","sequence":"additional","affiliation":[{"name":"Duke University, Durham, NC"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2008,7,25]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"Agilent 93000. 2008. Agilent 93000 Multi-Port Testing User Manual revision 4.0.0.  Agilent 93000. 2008. Agilent 93000 Multi-Port Testing User Manual revision 4.0.0."},{"key":"e_1_2_1_2_1","unstructured":"Agilent Technologies. 2002. Winning in the SoC market available online at: http:\/\/cp.literature.agilent.com\/litweb\/pdf\/5988-7344EN.pdf.  Agilent Technologies. 2002. Winning in the SoC market available online at: http:\/\/cp.literature.agilent.com\/litweb\/pdf\/5988-7344EN.pdf."},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/371254.371258"},{"volume-title":"Proceedings of the International Test Conference, 111--120","author":"Chickermane P. G. V.","key":"e_1_2_1_4_1","unstructured":"Chickermane , P. G. V. , Gregor , S. , and Pierre , T. S . 2001. A building block BIST methodology for SoC designs: A case study . In Proceedings of the International Test Conference, 111--120 . Chickermane, P. G. V., Gregor, S., and Pierre, T. S. 2001. A building block BIST methodology for SoC designs: A case study. In Proceedings of the International Test Conference, 111--120."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.585217"},{"volume-title":"Proceedings of the International Test Conference, 1169--1175","author":"Dorsch R.","key":"e_1_2_1_6_1","unstructured":"Dorsch , R. , Rivera , R. H. , Wunderlich , H. J. , and Fischer , M . 2002. Adapting an SoC to ATE concurrent test capabilities . In Proceedings of the International Test Conference, 1169--1175 . Dorsch, R., Rivera, R. H., Wunderlich, H. J., and Fischer, M. 2002. Adapting an SoC to ATE concurrent test capabilities. In Proceedings of the International Test Conference, 1169--1175."},{"volume-title":"Proceedings of the DATE Designers' Forum, 108--113","author":"Goel S. K.","key":"e_1_2_1_7_1","unstructured":"Goel , S. K. , Chiu , K. , Marinissen , E. J. , Nguyen , T. , and Oostdijk , S . 2004. Test infrastructure design for the Nexperia#8482; home platform pnx8550 system chip . In Proceedings of the DATE Designers' Forum, 108--113 . Goel, S. K., Chiu, K., Marinissen, E. J., Nguyen, T., and Oostdijk, S. 2004. Test infrastructure design for the Nexperia#8482; home platform pnx8550 system chip. In Proceedings of the DATE Designers' Forum, 108--113."},{"volume-title":"Proceedings of the International Test Conference, 529--538","author":"Goel S. K.","key":"e_1_2_1_8_1","unstructured":"Goel , S. K. and Marinissen , E. J . 2002. Effective and efficient test architecture design for SoCs . In Proceedings of the International Test Conference, 529--538 . Goel, S. K. and Marinissen, E. J. 2002. Effective and efficient test architecture design for SoCs. In Proceedings of the International Test Conference, 529--538."},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.818376"},{"volume-title":"Proceedings of the International Test Conference, 74--82","author":"Huang Y.","key":"e_1_2_1_10_1","unstructured":"Huang , Y. , Reddy , S. M. , Cheng , W. T. , Reuter , P. , Mukherjee , N. , Tsai , C. C. , Samman , O. , and Zaidan , Y . 2002. Optimal core wrapper width selection and SoC test scheduling based on 3-D bin packing algorithm . In Proceedings of the International Test Conference, 74--82 . Huang, Y., Reddy, S. M., Cheng, W. T., Reuter, P., Mukherjee, N., Tsai, C. C., Samman, O., and Zaidan, Y. 2002. Optimal core wrapper width selection and SoC test scheduling based on 3-D bin packing algorithm. In Proceedings of the International Test Conference, 74--82."},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.801102"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.810737"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2003.1252857"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1023\/A:1014916913577"},{"key":"e_1_2_1_15_1","unstructured":"Khoche A. 2001. Agilent corporation. Private communication.  Khoche A. 2001. Agilent corporation. Private communication."},{"volume-title":"Proceedings of the Asian Test Symposium, 259--264","author":"Larsson E.","key":"e_1_2_1_16_1","unstructured":"Larsson , E. and Peng , Z . 2001. Test scheduling and scan division under power constraint . In Proceedings of the Asian Test Symposium, 259--264 . Larsson, E. and Peng, Z. 2001. Test scheduling and scan division under power constraint. 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