{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:36:31Z","timestamp":1750307791981,"version":"3.41.0"},"reference-count":29,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2008,6,1]],"date-time":"2008-06-01T00:00:00Z","timestamp":1212278400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100000266","name":"Engineering and Physical Sciences Research Council","doi-asserted-by":"publisher","award":["EP\/D062322\/1EP\/C540481\/1"],"award-info":[{"award-number":["EP\/D062322\/1EP\/C540481\/1"]}],"id":[{"id":"10.13039\/501100000266","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2008,6]]},"abstract":"<jats:p>\n            The multivariate Gaussian distribution is often used to model correlations between stochastic time-series, and can be used to explore the effect of these correlations across\n            <jats:italic>N<\/jats:italic>\n            time-series in Monte-Carlo simulations. However, generating random correlated vectors is an\n            <jats:italic>O<\/jats:italic>\n            (\n            <jats:italic>N<\/jats:italic>\n            <jats:sup>2<\/jats:sup>\n            ) process, and quickly becomes a computational bottleneck in software simulations. This article presents an efficient method for generating vectors in parallel hardware, using\n            <jats:italic>N<\/jats:italic>\n            parallel pipelined components to generate a new vector every\n            <jats:italic>N<\/jats:italic>\n            cycles. This method maps well to the embedded block RAMs and multipliers in contemporary FPGAs, particularly as extensive testing shows that the limited bit-width arithmetic does not reduce the statistical quality of the generated vectors. An implementation of the architecture in the Virtex-4 architecture achieves a 500MHz clock-rate, and can support vector lengths up to 512 in the largest devices. The combination of a high clock-rate and parallelism provides a significant performance advantage over conventional processors, with an xc4vsx55 device at 500MHz providing a 200 times speedup over an Opteron 2.6GHz using an AMD optimised BLAS package. In a case study in Delta-Gamma Value-at Risk, an RC2000 accelerator card using an xc4vsx55 at 400MHz is 26 times faster than a quad Opteron 2.6GHz SMP.\n          <\/jats:p>","DOI":"10.1145\/1371579.1371584","type":"journal-article","created":{"date-parts":[[2009,1,13]],"date-time":"2009-01-13T13:15:48Z","timestamp":1231852548000},"page":"1-29","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":24,"title":["Multivariate Gaussian Random Number Generation Targeting Reconfigurable Hardware"],"prefix":"10.1145","volume":"1","author":[{"given":"David B.","family":"Thomas","sequence":"first","affiliation":[{"name":"Imperial College London"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wayne","family":"Luk","sequence":"additional","affiliation":[{"name":"Imperial College London"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2008,6]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"Advanced Micro Devices 2006. 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George M. and Alfke P. 2001. Linear feedback shift registers in Virtex devices. Tech. rep. Xilinx Inc."},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.859562"},{"key":"e_1_2_1_10_1","doi-asserted-by":"crossref","unstructured":"L'Ecuyer P. and Simard R. 2007. TestU01 random number test suite. www.iro.umontreal.ca\/ simardr\/indexe.html. L'Ecuyer P. and Simard R. 2007. TestU01 random number test suite. www.iro.umontreal.ca\/ simardr\/indexe.html.","DOI":"10.1145\/1268776.1268777"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2006.81"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2004.106"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.853615"},{"key":"e_1_2_1_14_1","unstructured":"Marsaglia G. 1999. Random numbers for C: The END? Posted to sci.crypt.random-numbers on 20th January 1999. Marsaglia G. 1999. Random numbers for C: The END? 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B.","key":"e_1_2_1_20_1"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2006.39"},{"volume-title":"Proceedings of the International Conference on Field Programmable Logic and Applications. 1--6.","author":"Thomas D. B.","key":"e_1_2_1_22_1"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2007.57"},{"key":"e_1_2_1_24_1","unstructured":"Xilinx Inc. 2000. Virtex-II platform FPGAs: Complete data sheet. Xilinx Inc. Xilinx Inc. 2000. Virtex-II platform FPGAs: Complete data sheet. Xilinx Inc."},{"key":"e_1_2_1_25_1","unstructured":"Xilinx Inc. 2002. Additive white Gaussian noise (AWGN) core. Tech. rep. Xilinx Inc. Xilinx Inc. 2002. Additive white Gaussian noise (AWGN) core. Tech. rep. Xilinx Inc."},{"key":"e_1_2_1_26_1","unstructured":"Xilinx Inc. 2005. XtremeDSP for Virtex-4 FPGAs User Guide. Xilinx Inc. Xilinx Inc. 2005. XtremeDSP for Virtex-4 FPGAs User Guide. Xilinx Inc."},{"key":"e_1_2_1_27_1","unstructured":"Xilinx Inc. 2006. Virtex-4---Why are the FIFO16 flags not working correctly? Tech. rep. AR22462. Xilinx Inc. 2006. Virtex-4---Why are the FIFO16 flags not working correctly? Tech. rep. AR22462."},{"volume-title":"Proceedings of the International Conference on Field Programmable Logic and Applications. IEEE Computer Society Press, 275--280","author":"Zhang G. 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