{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:36:51Z","timestamp":1750307811491,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":18,"publisher":"ACM","license":[{"start":{"date-parts":[[2008,6,7]],"date-time":"2008-06-07T00:00:00Z","timestamp":1212796800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2008,6,7]]},"DOI":"10.1145\/1375527.1375540","type":"proceedings-article","created":{"date-parts":[[2008,6,10]],"date-time":"2008-06-10T14:13:22Z","timestamp":1213107202000},"page":"63-72","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["An approach for adaptive DRAM temperature and power management"],"prefix":"10.1145","author":[{"given":"Song","family":"Liu","sequence":"first","affiliation":[{"name":"Northwestern University, Evanston, IL, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Seda","family":"Ogrenci Memik","sequence":"additional","affiliation":[{"name":"Northwestern University, Evanston, IL, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yu","family":"Zhang","sequence":"additional","affiliation":[{"name":"Northwestern University, Evanston, IL, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gokhan","family":"Memik","sequence":"additional","affiliation":[{"name":"Northwestern University, Evanston, IL, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2008,6,7]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2006.82"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.966492"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/383082.383118"},{"journal-title":"Intel Technology Journal","year":"2006","author":"Iyer J.","key":"e_1_3_2_1_4_1"},{"key":"e_1_3_2_1_5_1","unstructured":"JEDEC FBDIMM Specification: DDR2 SDRAM Fully Buffered DIMM (FBDIMM) Design Specification http:\/\/www.jedec.org\/download\/search\/JESD2051.pdf.  JEDEC FBDIMM Specification: DDR2 SDRAM Fully Buffered DIMM (FBDIMM) Design Specification http:\/\/www.jedec.org\/download\/search\/JESD2051.pdf."},{"key":"e_1_3_2_1_6_1","unstructured":"JEDEC FBDIMM: Advanced Memory Buffer (AMB) http:\/\/www.jedec.org\/download\/search\/JESD82-20.pdf.  JEDEC FBDIMM: Advanced Memory Buffer (AMB) http:\/\/www.jedec.org\/download\/search\/JESD82-20.pdf."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379007"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2005.846412"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250701"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2007.363740"},{"key":"e_1_3_2_1_11_1","unstructured":"Micron Calculating Memory System Power for DDR2.  Micron Calculating Memory System Power for DDR2."},{"key":"e_1_3_2_1_12_1","unstructured":"Micron DDR2 SDRAM FBDIMM http:\/\/download.micron.com\/pdf\/datasheets\/modules\/ddr2\/HTF18C128_256x72FD.pdf.  Micron DDR2 SDRAM FBDIMM http:\/\/download.micron.com\/pdf\/datasheets\/modules\/ddr2\/HTF18C128_256x72FD.pdf."},{"key":"e_1_3_2_1_13_1","unstructured":"Micron DDR2 SDRAM http:\/\/download.micron.com\/pdf\/datasheets\/dram\/ddr2\/512MbDDR2.pdf.  Micron DDR2 SDRAM http:\/\/download.micron.com\/pdf\/datasheets\/dram\/ddr2\/512MbDDR2.pdf."},{"key":"e_1_3_2_1_14_1","unstructured":"Micron System Power Calculator http:\/\/www.micron.com\/support\/designsupport\/tools\/powercalc\/powercalc.aspx.  Micron System Power Calculator http:\/\/www.micron.com\/support\/designsupport\/tools\/powercalc\/powercalc.aspx."},{"key":"e_1_3_2_1_15_1","unstructured":"Rambus RDRAM in www.rambus.com.  Rambus RDRAM in www.rambus.com."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.22"},{"key":"e_1_3_2_1_17_1","unstructured":"Shivakumar P. and N.P. Jouppi CACTI 3.0: An Integrated Cache Timing Power and Area Model WRL Research Report.  Shivakumar P. and N.P. Jouppi CACTI 3.0: An Integrated Cache Timing Power and Area Model WRL Research Report."},{"volume-title":"Standard Performance Evaluation Corporation. SPEC CPU2000 .","key":"e_1_3_2_1_18_1"}],"event":{"name":"ICS08: International Conference on Supercomputing","sponsor":["ACM Association for Computing Machinery","SIGARCH ACM Special Interest Group on Computer Architecture"],"location":"Island of Kos Greece","acronym":"ICS08"},"container-title":["Proceedings of the 22nd annual international conference on Supercomputing"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1375527.1375540","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1375527.1375540","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:57:36Z","timestamp":1750255056000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1375527.1375540"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,6,7]]},"references-count":18,"alternative-id":["10.1145\/1375527.1375540","10.1145\/1375527"],"URL":"https:\/\/doi.org\/10.1145\/1375527.1375540","relation":{},"subject":[],"published":{"date-parts":[[2008,6,7]]},"assertion":[{"value":"2008-06-07","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}