{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:37:10Z","timestamp":1750307830505,"version":"3.41.0"},"reference-count":20,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2008,7,1]],"date-time":"2008-07-01T00:00:00Z","timestamp":1214870400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2008,7]]},"abstract":"<jats:p>Network processors can be categorized into two types, the coprocessors-centric model in which data-plane is handled by coprocessors, and the core-centric model in which the core processes most of the data-plane packets yet offloading some tasks to coprocessors. While the former has been properly explored over various applications, research regarding the latter remain limited. Based on the previous experience of prototyping the virtual private network (VPN) over the IXP425 network processor, this work aims to derive design implications for the core-centric model performing computational intensive applications. From system and IC vendors' perspectives, the continuous-time Markov chain and Petri net simulations are adopted to explore this architecture. Analytical results prove to be quite inline with those of the simulation and implementation. With subsequent investigation, we find that appropriate process run lengths can improve the effective core utilization by 2.26 times, and by offloading the throughput boosts 7.5 times. The results also suggest single-process programming, since context-switch overhead impacts considerably on the performance.<\/jats:p>","DOI":"10.1145\/1376804.1376809","type":"journal-article","created":{"date-parts":[[2008,8,5]],"date-time":"2008-08-05T13:35:10Z","timestamp":1217943310000},"page":"1-15","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Modeling and analysis of core-centric network processors"],"prefix":"10.1145","volume":"7","author":[{"given":"Yi-Neng","family":"Lin","sequence":"first","affiliation":[{"name":"National Chiao Tung University, Hsinchu, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ying-Dar","family":"Lin","sequence":"additional","affiliation":[{"name":"National Chiao Tung University, Hsinchu, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuan-Cheng","family":"Lai","sequence":"additional","affiliation":[{"name":"National Taiwan University of Science and Technology, Taipei, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kuo-Kun","family":"Tseng","sequence":"additional","affiliation":[{"name":"National Chiao Tung University, Hsinchu, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2008,8]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"Braun T. G\u00fcnter M. Kasumi M. and Khalil I. 1999. Virtual private network architecture. Technical rep. IAM-99-001 CATI.  Braun T. G\u00fcnter M. Kasumi M. and Khalil I. 1999. Virtual private network architecture. Technical rep. IAM-99-001 CATI."},{"volume-title":"Proceedings of the 3rd Workshop on Network Processors and Applications (NP3)","author":"Clark C.","key":"e_1_2_1_2_1"},{"volume-title":"Proceedings of the 2nd International Conference on Testbeds and Research Infrastructures for the Development of Networks and Communities (TRIDENTCOM).","author":"Comer D.","key":"e_1_2_1_3_1"},{"volume-title":"Proceedings of the Network Processor Workshop in Conjunction with 8th International Symposium on High Performance Computer Architecture (NP1).","author":"Crowley P.","key":"e_1_2_1_4_1"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1105734.1105738"},{"key":"e_1_2_1_6_1","unstructured":"Intel IXP425 Network Processor. http:\/\/www.intel.com\/design\/network\/products\/npfamily\/ixp425.htm.  Intel IXP425 Network Processor. http:\/\/www.intel.com\/design\/network\/products\/npfamily\/ixp425.htm."},{"key":"e_1_2_1_7_1","unstructured":"Intel IXP2400 Network Processor. http:\/\/www.intel.com\/design\/network\/products\/npfamily\/ixp2400.htm.  Intel IXP2400 Network Processor. http:\/\/www.intel.com\/design\/network\/products\/npfamily\/ixp2400.htm."},{"volume-title":"Network Processors: Architectures, Protocols and Platforms (Telecom Engineering)","year":"2003","author":"Lekkas P. C.","key":"e_1_2_1_8_1"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/MNET.2003.1220693"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2005.58"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.jss.2007.01.032"},{"volume-title":"Proceedings of the 15th International Conference on Computer Communications and Networks (IC3N'06)","author":"Lu J.","key":"e_1_2_1_12_1"},{"key":"e_1_2_1_13_1","unstructured":"Microsoft TechNet. http:\/\/www.microsoft.com\/technet\/prodtechnol\/windows2000serv\/reskit\/core\/fned_ana_trrf.mspx?mfr=true.  Microsoft TechNet. http:\/\/www.microsoft.com\/technet\/prodtechnol\/windows2000serv\/reskit\/core\/fned_ana_trrf.mspx?mfr=true."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.24143"},{"key":"e_1_2_1_15_1","unstructured":"Nussbaum D. Fedorova A. and Small C. 2004. An Overview of the Sam CMT simulator kit. Technical rep. Sun Microsystems.   Nussbaum D. Fedorova A. and Small C. 2004. An Overview of the Sam CMT simulator kit. Technical rep. Sun Microsystems."},{"volume-title":"Proceedings of the International Conference on Applications and Theory of Petri Nets.","author":"Ratzer A.V.","key":"e_1_2_1_16_1"},{"key":"e_1_2_1_17_1","unstructured":"Smith J. M. S. 1997. Application-Specific Integrated Circuits. Addison-Wesley Reading MA.  Smith J. M. S. 1997. Application-Specific Integrated Circuits. Addison-Wesley Reading MA."},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2004.54"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2006.75"},{"volume-title":"Proceedings of the Workshop on Practical Use of Colored Petri Nets and Design\/CPN.","author":"Zuberek W. M.","key":"e_1_2_1_20_1"}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1376804.1376809","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1376804.1376809","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:57:55Z","timestamp":1750255075000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1376804.1376809"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,7]]},"references-count":20,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2008,7]]}},"alternative-id":["10.1145\/1376804.1376809"],"URL":"https:\/\/doi.org\/10.1145\/1376804.1376809","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"type":"print","value":"1539-9087"},{"type":"electronic","value":"1558-3465"}],"subject":[],"published":{"date-parts":[[2008,7]]},"assertion":[{"value":"2007-07-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2008-03-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2008-08-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}