{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,28]],"date-time":"2025-06-28T07:03:21Z","timestamp":1751094201248,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":33,"publisher":"ACM","license":[{"start":{"date-parts":[[2008,6,14]],"date-time":"2008-06-14T00:00:00Z","timestamp":1213401600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2008,6,14]]},"DOI":"10.1145\/1378533.1378535","type":"proceedings-article","created":{"date-parts":[[2008,6,17]],"date-time":"2008-06-17T13:49:02Z","timestamp":1213710542000},"page":"1-10","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":21,"title":["Utilizing shared data in chip multiprocessors with the Nahalal architecture"],"prefix":"10.1145","author":[{"given":"Zvika","family":"Guz","sequence":"first","affiliation":[{"name":"Technion - Israel Institute of Technology, Haifa, Israel"}]},{"given":"Idit","family":"Keidar","sequence":"additional","affiliation":[{"name":"Technion - Israel Institute of Technology, Haifa, Israel"}]},{"given":"Avinoam","family":"Kolodny","sequence":"additional","affiliation":[{"name":"Technion - Israel Institute of Technology, Haifa, Israel"}]},{"given":"Uri C.","family":"Weiser","sequence":"additional","affiliation":[{"name":"Technion - Israel Institute of Technology, Haifa, Israel"}]}],"member":"320","published-online":{"date-parts":[[2008,6,14]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"April","author":"Mai K.","year":"2001","unstructured":"Ho, K. Mai , and M. Horowitz , '' The future of wires,'' Proceedings of IEEE,89(4) , April 2001 .]] Ho, K. Mai, and M. Horowitz, ''The future of wires,'' Proceedings of IEEE,89(4), April 2001.]]"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.612253"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339691"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.5555\/786453.786719"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605420"},{"issue":"02","key":"e_1_3_2_1_6_1","article-title":"Introduction to Intel\u00ae Core","volume":"10","author":"Mendelson A.","year":"2006","unstructured":"Gochman, A. Mendelson , A. Naveh , A, and E. Rotem , \" Introduction to Intel\u00ae Core \" Duo Processor Architecture,\" Intel Technology Journal , Volume 10 , Issue 02 . May 2006 .]] Gochman, A. Mendelson, A. Naveh, A, and E. Rotem, \"Introduction to Intel\u00ae Core\" Duo Processor Architecture,\" Intel Technology Journal, Volume 10, Issue 02. May 2006.]]","journal-title":"Duo Processor Architecture,\" Intel Technology Journal"},{"key":"e_1_3_2_1_7_1","unstructured":"AMD white paper ''Key Architectural Features AMD Athlon\u2122 64 X2 Dual-Core and AMD Athlon\u2122 X2 Dual-Core Processors '' http:\/\/www.amd.com\/gb-uk\/Processors\/ProductInformation\/0 30_118_9485_13041%5E13043 00.html]]  AMD white paper ''Key Architectural Features AMD Athlon\u2122 64 X2 Dual-Core and AMD Athlon\u2122 X2 Dual-Core Processors '' http:\/\/www.amd.com\/gb-uk\/Processors\/ProductInformation\/0 30_118_9485_13041%5E13043 00.html]]"},{"key":"e_1_3_2_1_8_1","unstructured":"AMD technical articles ''Barcelona's Innovative Architecture Is Driven by a New Shared Cache '' http:\/\/developer.amd.com\/article_print.jsp?id=173]]  AMD technical articles ''Barcelona's Innovative Architecture Is Driven by a New Shared Cache '' http:\/\/developer.amd.com\/article_print.jsp?id=173]]"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/216585.216588"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.21"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1088149.1088154"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2007.6"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.10"},{"volume-title":"Garden Cities of To-Morrow","year":"1902","key":"e_1_3_2_1_14_1","unstructured":"Howard , '' Garden Cities of To-Morrow ,'' London : Swan Sonnenschein & Co. Ltd , 1902 ]] Howard, ''Garden Cities of To-Morrow,'' London: Swan Sonnenschein & Co. Ltd, 1902]]"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2006.6"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.17"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.39"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1248377.1248398"},{"key":"e_1_3_2_1_19_1","volume-title":"Workshop on Chip Multiprocessor Memory Systems and Interconnects","author":"Cho S.","year":"2007","unstructured":"Jin and S. Cho , '' Better than the Two: Exceeding Private and Shared Caches via Two-Dimensional Page Coloring '', in Workshop on Chip Multiprocessor Memory Systems and Interconnects , 2007 .]] Jin and S. Cho, ''Better than the Two: Exceeding Private and Shared Caches via Two-Dimensional Page Coloring'', in Workshop on Chip Multiprocessor Memory Systems and Interconnects, 2007.]]"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250670"},{"key":"e_1_3_2_1_21_1","volume-title":"April","author":"Sivasubramaniam A.","year":"2006","unstructured":"Liu, A. Sivasubramaniam , M. Kandemir , and M. J. Irwin , '' Enhancing L2 organization for CMPs with a center cell,'' IPDPS'06 , April 2006 .]] Liu, A. Sivasubramaniam, M. Kandemir, and M. J. Irwin, ''Enhancing L2 organization for CMPs with a center cell,'' IPDPS'06, April 2006.]]"},{"key":"e_1_3_2_1_22_1","volume-title":"Better than the two: Exceeding private and shared caches via two-dimensional page coloring,'' in Workshop on Chip Multiprocessor Memory Systems and Interconnects","author":"Cho S.","year":"2007","unstructured":"Jin, and S. Cho , '' Better than the two: Exceeding private and shared caches via two-dimensional page coloring,'' in Workshop on Chip Multiprocessor Memory Systems and Interconnects , 2007 .]] Jin, and S. Cho, ''Better than the two: Exceeding private and shared caches via two-dimensional page coloring,'' in Workshop on Chip Multiprocessor Memory Systems and Interconnects, 2007.]]"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.53"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.982916"},{"key":"e_1_3_2_1_25_1","volume-title":"7th Workshop on Complexity-Effective Design (WCED)","author":"Barrus S.","year":"2006","unstructured":"Ricci, S. Barrus , D. Gebhardt , and R. Balasubramonian , '' Leveraging Bloom Filters for Smart Search Within NUCA Caches '', 7th Workshop on Complexity-Effective Design (WCED) , June 2006 .]] Ricci, S. Barrus, D. Gebhardt, and R. Balasubramonian, ''Leveraging Bloom Filters for Smart Search Within NUCA Caches'', 7th Workshop on Complexity-Effective Design (WCED), June 2006.]]"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/223982.223990"},{"key":"e_1_3_2_1_27_1","first-page":"1","volume-title":"SPEComp: A New Benchmark Suite for Measuring Parallel Computer Performance. In Workshop on OpenMP Applications and Tools","author":"Domeika M.","year":"2001","unstructured":"Aslot, M. Domeika , R. Eigenmann , G. Gaertner , W. Jones , and B. Parady . SPEComp: A New Benchmark Suite for Measuring Parallel Computer Performance. In Workshop on OpenMP Applications and Tools , pages 1 -- 10 , July 2001 .]] Aslot, M. Domeika, R. Eigenmann, G. Gaertner, W. Jones, and B. Parady. SPEComp: A New Benchmark Suite for Measuring Parallel Computer Performance. In Workshop on OpenMP Applications and Tools, pages 1--10, July 2001.]]"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/277851.277897"},{"key":"e_1_3_2_1_29_1","unstructured":"http:\/\/www.zeus.com\/products\/zws\/]]  http:\/\/www.zeus.com\/products\/zws\/]]"},{"key":"e_1_3_2_1_30_1","unstructured":"http:\/\/www.spec.org\/jbb2000\/]]  http:\/\/www.spec.org\/jbb2000\/]]"},{"key":"e_1_3_2_1_31_1","unstructured":"J. Marathe M. F. Spear C. Heriot A. Acharya D. Eisenstat W. N. Scherer III and M. L. Scott \"Lowering the Overhead of Nonblocking Software Transactional Memory \" TRANSACT 2006]]  J. Marathe M. F. Spear C. Heriot A. Acharya D. Eisenstat W. N. Scherer III and M. L. Scott \"Lowering the Overhead of Nonblocking Software Transactional Memory \" TRANSACT 2006]]"},{"key":"e_1_3_2_1_32_1","volume-title":"June","author":"Tullsen D.","year":"2004","unstructured":"Kumar, D. Tullsen , P. Ranganathan , N. Jouppi , and K. Farkas . \" Single-ISA Heterogeneous Multi-core Architectures for Multithreaded Workload Performance.\" ISCA-31 , June 2004 .]] Kumar, D. Tullsen, P. Ranganathan, N. Jouppi, and K. Farkas. \"Single-ISA Heterogeneous Multi-core Architectures for Multithreaded Workload Performance.\" ISCA-31, June 2004.]]"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065010.1065034"}],"event":{"name":"SPAA08: 20th ACM Symposium on Parallelism in Algorithms and Architectures","sponsor":["ACM Association for Computing Machinery","SIGACT ACM Special Interest Group on Algorithms and Computation Theory","SIGARCH ACM Special Interest Group on Computer Architecture"],"location":"Munich Germany","acronym":"SPAA08"},"container-title":["Proceedings of the twentieth annual symposium on Parallelism in algorithms and architectures"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1378533.1378535","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1378533.1378535","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T14:57:53Z","timestamp":1750258673000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1378533.1378535"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,6,14]]},"references-count":33,"alternative-id":["10.1145\/1378533.1378535","10.1145\/1378533"],"URL":"https:\/\/doi.org\/10.1145\/1378533.1378535","relation":{},"subject":[],"published":{"date-parts":[[2008,6,14]]},"assertion":[{"value":"2008-06-14","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}