{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T12:11:13Z","timestamp":1763467873934,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":28,"publisher":"ACM","license":[{"start":{"date-parts":[[2008,6,8]],"date-time":"2008-06-08T00:00:00Z","timestamp":1212883200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000144","name":"Division of Computer and Network Systems","doi-asserted-by":"publisher","award":["CCR-0306682CNS-0720881"],"award-info":[{"award-number":["CCR-0306682CNS-0720881"]}],"id":[{"id":"10.13039\/100000144","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CCR-0306682CNS-0720881"],"award-info":[{"award-number":["CCR-0306682CNS-0720881"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2008,6,8]]},"DOI":"10.1145\/1391469.1391478","type":"proceedings-article","created":{"date-parts":[[2008,7,30]],"date-time":"2008-07-30T12:09:58Z","timestamp":1217419798000},"page":"24-29","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["FPGA area reduction by multi-output function based sequential resynthesis"],"prefix":"10.1145","author":[{"given":"Yu","family":"Hu","sequence":"first","affiliation":[{"name":"University of California, Los Angeles"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Victor","family":"Shih","sequence":"additional","affiliation":[{"name":"University of California, Los Angeles"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rupak","family":"Majumdar","sequence":"additional","affiliation":[{"name":"University of California, Los Angeles"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lei","family":"He","sequence":"additional","affiliation":[{"name":"University of California, Los Angeles"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2008,6,8]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Complexity of the lookup-table minimization problem for fpga technology mapping,\" TCAD","author":"Farrahi A.","year":"1994","unstructured":"A. Farrahi and M. Sarrafzadeh , \" Complexity of the lookup-table minimization problem for fpga technology mapping,\" TCAD , 1994 . A. Farrahi and M. Sarrafzadeh, \"Complexity of the lookup-table minimization problem for fpga technology mapping,\" TCAD, 1994."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_2_1","DOI":"10.1145\/157485.164675"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_3_1","DOI":"10.1145\/201310.201322"},{"key":"e_1_3_2_1_4_1","volume-title":"Heuristics for area minimization in lut-based fpga technology mapping,\" IWLS","author":"Manohararajah V.","year":"2004","unstructured":"V. Manohararajah , S. D. Brown , and Z. G. Vranesic , \" Heuristics for area minimization in lut-based fpga technology mapping,\" IWLS , 2004 . V. Manohararajah, S. D. Brown, and Z. G. Vranesic, \"Heuristics for area minimization in lut-based fpga technology mapping,\" IWLS, 2004."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_5_1","DOI":"10.1109\/ICCAD.2004.1382677"},{"unstructured":"\"Abc: A system for sequential synthesis and verification \" in http:\/\/www.eecs.berkeley.edu\/alumni\/abc\/.  \"Abc: A system for sequential synthesis and verification \" in http:\/\/www.eecs.berkeley.edu\/alumni\/abc\/.","key":"e_1_3_2_1_6_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_7_1","DOI":"10.1145\/1117201.1117208"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_8_1","DOI":"10.1145\/1117201.1117207"},{"key":"e_1_3_2_1_9_1","volume-title":"algorithms for cycle-time minimization,\" TCAD","author":"Micheli G. D.","year":"1991","unstructured":"G. D. Micheli , \"Synchronous logic synthesis : algorithms for cycle-time minimization,\" TCAD , 1991 . G. D. Micheli, \"Synchronous logic synthesis: algorithms for cycle-time minimization,\" TCAD, 1991."},{"key":"e_1_3_2_1_10_1","volume-title":"Dag-aware aig rewriting,\" DAC","author":"Mishchenko A.","year":"2005","unstructured":"A. Mishchenko , S. Chatterjee , and R. Brayton , \" Dag-aware aig rewriting,\" DAC , 2005 . A. Mishchenko, S. Chatterjee, and R. Brayton, \"Dag-aware aig rewriting,\" DAC, 2005."},{"key":"e_1_3_2_1_11_1","volume-title":"Retiming and resynthesis: Optimizing sequential networks with combinational techniques,\" TCAD","author":"Malik S.","year":"1991","unstructured":"S. Malik , E. Sentovich , R. Brayton , and A. Sangiovanni-Vincentelli , \" Retiming and resynthesis: Optimizing sequential networks with combinational techniques,\" TCAD , 1991 . S. Malik, E. Sentovich, R. Brayton, and A. Sangiovanni-Vincentelli, \"Retiming and resynthesis: Optimizing sequential networks with combinational techniques,\" TCAD, 1991."},{"key":"e_1_3_2_1_12_1","volume-title":"Sequential rewriting,\" IWLS","author":"Brayton R.","year":"2007","unstructured":"R. Brayton and A. Mishchenko , \" Sequential rewriting,\" IWLS , 2007 . R. Brayton and A. Mishchenko, \"Sequential rewriting,\" IWLS, 2007."},{"key":"e_1_3_2_1_13_1","volume-title":"Logic decomposition during technology mapping,\" TCAD","author":"Lehman E.","year":"1997","unstructured":"E. Lehman , Y. Watanabe , J. Grodstein , and H. Harkness , \" Logic decomposition during technology mapping,\" TCAD , 1997 . E. Lehman, Y. Watanabe, J. Grodstein, and H. Harkness, \"Logic decomposition during technology mapping,\" TCAD, 1997."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_14_1","DOI":"10.1145\/775832.775871"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_15_1","DOI":"10.1145\/1065579.1065693"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_16_1","DOI":"10.1145\/1216919.1216944"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_17_1","DOI":"10.1145\/264995.264996"},{"key":"e_1_3_2_1_18_1","volume-title":"Exploiting symmetry in satbased boolean matching for heterogeneous fpga technology mapping,\" ICCAD","author":"Hu Y.","year":"2007","unstructured":"Y. Hu , V. Shih , R. Majumdar , and L. He , \" Exploiting symmetry in satbased boolean matching for heterogeneous fpga technology mapping,\" ICCAD , 2007 . Y. Hu, V. Shih, R. Majumdar, and L. He, \"Exploiting symmetry in satbased boolean matching for heterogeneous fpga technology mapping,\" ICCAD, 2007."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_19_1","DOI":"10.1145\/1146909.1147034"},{"key":"e_1_3_2_1_20_1","volume-title":"Design, synthesis and evaluation of heterogeneous fpga with mixed luts and macro-gates,\" ICCAD","author":"Hu Y.","year":"2007","unstructured":"Y. Hu , S. Das , S. Trimberger , and L. He , \" Design, synthesis and evaluation of heterogeneous fpga with mixed luts and macro-gates,\" ICCAD , 2007 . Y. Hu, S. Das, S. Trimberger, and L. He, \"Design, synthesis and evaluation of heterogeneous fpga with mixed luts and macro-gates,\" ICCAD, 2007."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_21_1","DOI":"10.1109\/DATE.2005.264"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_22_1","DOI":"10.1145\/296399.296425"},{"key":"e_1_3_2_1_23_1","volume-title":"Retiming synchronous circuitry,\" Algorithmica","author":"Leiserson C. E.","year":"1991","unstructured":"C. E. Leiserson and J. B. Saxe , \" Retiming synchronous circuitry,\" Algorithmica , 1991 . C. E. Leiserson and J. B. Saxe, \"Retiming synchronous circuitry,\" Algorithmica, 1991."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_24_1","DOI":"10.1145\/1055137.1055156"},{"unstructured":"N. Een and N. Sorensso http:\/\/www.cs.chalmers.se\/Cs\/Research\/ FormalMethods\/MiniSat\/MiniSat.html.  N. Een and N. Sorensso http:\/\/www.cs.chalmers.se\/Cs\/Research\/ FormalMethods\/MiniSat\/MiniSat.html.","key":"e_1_3_2_1_25_1"},{"key":"e_1_3_2_1_26_1","volume-title":"MCNC Designers' Manual","author":"MCNC","year":"1993","unstructured":"MCNC , MCNC Designers' Manual , 1993 . MCNC, MCNC Designers' Manual, 1993."},{"unstructured":"\"Iwls 2005 benchmarks \" in http:\/\/iwls.org\/iwls2005\/benchmarks.html.  \"Iwls 2005 benchmarks \" in http:\/\/iwls.org\/iwls2005\/benchmarks.html.","key":"e_1_3_2_1_27_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_28_1","DOI":"10.1145\/275107.275118"}],"event":{"sponsor":["The EDA Consortium","IEEE\/CASS\/CANDE\/CEDA","SIGDA ACM Special Interest Group on Design Automation"],"acronym":"DAC '08","name":"DAC '08: The 45th Annual Design Automation Conference 2008","location":"Anaheim California"},"container-title":["Proceedings of the 45th annual Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1391469.1391478","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1391469.1391478","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:58:04Z","timestamp":1750255084000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1391469.1391478"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,6,8]]},"references-count":28,"alternative-id":["10.1145\/1391469.1391478","10.1145\/1391469"],"URL":"https:\/\/doi.org\/10.1145\/1391469.1391478","relation":{},"subject":[],"published":{"date-parts":[[2008,6,8]]},"assertion":[{"value":"2008-06-08","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}