{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:38:07Z","timestamp":1750307887544,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":28,"publisher":"ACM","license":[{"start":{"date-parts":[[2008,6,8]],"date-time":"2008-06-08T00:00:00Z","timestamp":1212883200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2008,6,8]]},"DOI":"10.1145\/1391469.1391680","type":"proceedings-article","created":{"date-parts":[[2008,7,30]],"date-time":"2008-07-30T12:09:58Z","timestamp":1217419798000},"page":"828-833","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":20,"title":["Scan chain clustering for test power reduction"],"prefix":"10.1145","author":[{"given":"Melanie","family":"Elm","sequence":"first","affiliation":[{"name":"Universitaet Stuttgart, Pfaffenwaldring, Stuttgart, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hans-Joachim","family":"Wunderlich","sequence":"additional","affiliation":[{"name":"Universitaet Stuttgart, Pfaffenwaldring, Stuttgart, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael E.","family":"Imhof","sequence":"additional","affiliation":[{"name":"Universitaet Stuttgart, Pfaffenwaldring, Stuttgart, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Christian G.","family":"Zoellin","sequence":"additional","affiliation":[{"name":"Universitaet Stuttgart, Pfaffenwaldring, Stuttgart, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jens","family":"Leenstra","sequence":"additional","affiliation":[{"name":"IBM Deutschland Entwicklung, Boeblingen, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nicolas","family":"Maeding","sequence":"additional","affiliation":[{"name":"IBM Deutschland Entwicklung, Boeblingen, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2008,6,8]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Y. Zorian \"A distributed BIST control scheme for complex VLSI devices \" in Proceedings of the 11th IEEE VLSI Test Symposium (VTS '93) 1993 pp. 4--9. Y. Zorian \"A distributed BIST control scheme for complex VLSI devices \" in Proceedings of the 11th IEEE VLSI Test Symposium (VTS '93) 1993 pp. 4--9."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/54.785836"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2002.1003802"},{"key":"e_1_3_2_1_4_1","first-page":"74","volume-title":"Optimal core wrapper width selection and SOC test scheduling based on 3-D bin packing algorithm,\" in Proceedings IEEE International Test Conference","author":"Huang Y.","year":"2002","unstructured":"Y. Huang , S. M. Reddy , W.-T. Cheng , P. Reuter , N. Mukherjee , C.-C. Tsai , O. Samman , and Y. Zaidan , \" Optimal core wrapper width selection and SOC test scheduling based on 3-D bin packing algorithm,\" in Proceedings IEEE International Test Conference , Baltimore, MD, USA , October 7--10, 2002 , pp. 74 -- 82 . Y. Huang, S. M. Reddy, W.-T. Cheng, P. Reuter, N. Mukherjee, C.-C. Tsai, O. Samman, and Y. Zaidan, \"Optimal core wrapper width selection and SOC test scheduling based on 3-D bin packing algorithm,\" in Proceedings IEEE International Test Conference, Baltimore, MD, USA, October 7--10, 2002, pp. 74--82."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2003.1214352"},{"key":"e_1_3_2_1_6_1","first-page":"77","article-title":"Minimized power consumption for scan-based BIST,\" in IEEE International Test Conference (ITC '99)","author":"Gerstendoerfer S.","year":"1999","unstructured":"S. Gerstendoerfer and H.-J. Wunderlich , \" Minimized power consumption for scan-based BIST,\" in IEEE International Test Conference (ITC '99) , NJ, USA, 27-- 30 Sept. , 1999 , pp. 77 -- 84 . S. Gerstendoerfer and H.-J. Wunderlich, \"Minimized power consumption for scan-based BIST,\" in IEEE International Test Conference (ITC '99), NJ, USA, 27--30 Sept., 1999, pp. 77--84.","journal-title":"NJ, USA, 27--"},{"key":"e_1_3_2_1_7_1","first-page":"30.3","volume-title":"Austin TX","author":"Huang Y.","year":"2005","unstructured":"Y. Huang , W. Cheng , and J. Rajski , \" Compressed pattern diagnosis for scan chain failures,\" in IEEE International Test Conference (ITC '05), 8--10 Nov ., Austin TX , 2005 , p. 30.3 . Y. Huang, W. Cheng, and J. Rajski, \"Compressed pattern diagnosis for scan chain failures,\" in IEEE International Test Conference (ITC '05), 8--10 Nov., Austin TX, 2005, p. 30.3."},{"key":"e_1_3_2_1_8_1","first-page":"319","volume-title":"USA","author":"Sankaralingam R.","year":"2001","unstructured":"R. Sankaralingam , N. A. Touba , and B. Pouya , \" Reducing power dissipation during test using scan chain disable,\" in 19th IEEE VLSI Test Symposium (VTS '01), 29 April - 3 May, Marina Del Rey, CA , USA , 2001 , pp. 319 -- 325 . R. Sankaralingam, N. A. Touba, and B. Pouya, \"Reducing power dissipation during test using scan chain disable,\" in 19th IEEE VLSI Test Symposium (VTS '01), 29 April - 3 May, Marina Del Rey, CA, USA, 2001, pp. 319--325."},{"key":"e_1_3_2_1_9_1","volume-title":"USA","author":"Zoellin C.","year":"2006","unstructured":"C. Zoellin , H.-J. Wunderlich , N. Maeding , and J. Leenstra , \" BIST power reduction using scan-chain disable in the Cell processor,\" in IEEE International Test Conference (ITC '06), Santa Clara, CA , USA , Oct. 24-26, 2006 . C. Zoellin, H.-J. Wunderlich, N. Maeding, and J. Leenstra, \"BIST power reduction using scan-chain disable in the Cell processor,\" in IEEE International Test Conference (ITC '06), Santa Clara, CA, USA, Oct. 24-26, 2006."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278614"},{"key":"e_1_3_2_1_11_1","first-page":"355","volume-title":"USA","author":"Butler K. M.","year":"2004","unstructured":"K. M. Butler , J. Saxena , T. Fryars , and G. Hetherington , \" Minimizing power consumption in scan testing: Pattern generation and DFT techniques,\" in IEEE International Test Conference (ITC '04), Oct. 26--28, Charlotte, NC , USA , 2004 , pp. 355 -- 364 . K. M. Butler, J. Saxena, T. Fryars, and G. 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Nicolici , \" Low power mixed-mode BIST based on mask pattern generation using dual LFSR re-seeding,\" in 20th International Conference on Computer Design (ICCD '02), VLSI in Computers and Processors, 16--18 Sept ., Freiburg , Germany , 2002 , pp. 474 -- 479 . P. M. Rosinger, B. M. Al-Hashimi, and N. Nicolici, \"Low power mixed-mode BIST based on mask pattern generation using dual LFSR re-seeding,\" in 20th International Conference on Computer Design (ICCD '02), VLSI in Computers and Processors, 16--18 Sept., Freiburg, Germany, 2002, pp. 474--479."},{"key":"e_1_3_2_1_14_1","first-page":"180","volume-title":"USA","author":"Lee J.","year":"2004","unstructured":"J. Lee and N. A. Touba , \" Low power test data compression based on LFSR reseeding,\" in 22nd IEEE International Conference on Computer Design: VLSI in Computers &amp; Processors (ICCD '04), 11--13 Oct., San Jose, CA , USA , 2004 , pp. 180 -- 185 . J. Lee and N. A. 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Virazel, \"Design of routing-constrained low power scan chains,\" in Design, Automation and Test in Europe (DATE '04), 16--20 Feb., Paris, France, 2004, pp. 62--67."},{"key":"e_1_3_2_1_18_1","first-page":"751","volume-title":"Integrating scan into hierarchical synthesis methodologies,\" in Proceedings IEEE International Test Conference (ITC '96), Test and Design Validity","author":"Beausang J.","year":"1996","unstructured":"J. Beausang , C. Ellingham , and M. Robinson , \" Integrating scan into hierarchical synthesis methodologies,\" in Proceedings IEEE International Test Conference (ITC '96), Test and Design Validity , Washington, DC, USA , October 20--25, 1996 , pp. 751 -- 756 . J. Beausang, C. Ellingham, and M. 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VLSI Design Laboratory , McGill University , 1989 . O. E. Cornelia and V. K. Agarwal, Conditional Stuck-at Fault Model for PLA Test Generation. VLSI Design Laboratory, McGill University, 1989."},{"key":"e_1_3_2_1_22_1","first-page":"446","volume-title":"USA","author":"Hamzaoglu I.","year":"1998","unstructured":"I. Hamzaoglu and J. H. Patel , \" New techniques for deterministic test pattern generation,\" in 16th IEEE VLSI Test Symposium (VTS '98), 28 April - 1 May, Princeton, NJ , USA , 1998 , pp. 446 -- 452 . I. Hamzaoglu and J. H. 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Lin , \" An efficient heuristic procedure for partitioning graphs.\" Bell System Technical Journal , February , vol. 49 , no. 2, pp. 291--307, 1970. B. W. Kernighan and S. Lin, \"An efficient heuristic procedure for partitioning graphs.\" Bell System Technical Journal, February, vol. 49, no. 2, pp. 291--307, 1970."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/309847.309954"},{"key":"e_1_3_2_1_27_1","first-page":"6.1","volume-title":"Austin TX","author":"Riley M.","year":"2005","unstructured":"M. Riley , L. Bushard , N. Chelstrom , N. Kiryu , and S. Ferguson , \" Testability features of the first-generation Cell processor,\" in Proceedings of the IEEE International Test Conference (ITC '05), 8--10 Nov ., Austin TX , 2005 , p. 6.1 . M. Riley, L. Bushard, N. Chelstrom, N. Kiryu, and S. Ferguson, \"Testability features of the first-generation Cell processor,\" in Proceedings of the IEEE International Test Conference (ITC '05), 8--10 Nov., Austin TX, 2005, p. 6.1."},{"key":"e_1_3_2_1_28_1","first-page":"442","volume-title":"USA","author":"Tang Y.","year":"2004","unstructured":"Y. Tang , H.-J. Wunderlich , H. Vranken , F. Hapke , M. Wittke , P. Engelke , I. Polian , and B. Becker , \" X-Masking during logic BIST and its impact on defect coverage,\" in IEEE International Test Conference (ITC '04), Oct. 25--28, Charlotte, NC , USA , 2004 , pp. 442 -- 451 . Y. Tang, H.-J. Wunderlich, H. Vranken, F. Hapke, M. Wittke, P. Engelke, I. Polian, and B. Becker, \"X-Masking during logic BIST and its impact on defect coverage,\" in IEEE International Test Conference (ITC '04), Oct. 25--28, Charlotte, NC, USA, 2004, pp. 442--451."}],"event":{"name":"DAC '08: The 45th Annual Design Automation Conference 2008","sponsor":["The EDA Consortium","IEEE\/CASS\/CANDE\/CEDA","SIGDA ACM Special Interest Group on Design Automation"],"location":"Anaheim California","acronym":"DAC '08"},"container-title":["Proceedings of the 45th annual Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1391469.1391680","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1391469.1391680","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T14:47:13Z","timestamp":1750258033000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1391469.1391680"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,6,8]]},"references-count":28,"alternative-id":["10.1145\/1391469.1391680","10.1145\/1391469"],"URL":"https:\/\/doi.org\/10.1145\/1391469.1391680","relation":{},"subject":[],"published":{"date-parts":[[2008,6,8]]},"assertion":[{"value":"2008-06-08","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}