{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:38:07Z","timestamp":1750307887385,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":22,"publisher":"ACM","license":[{"start":{"date-parts":[[2008,6,8]],"date-time":"2008-06-08T00:00:00Z","timestamp":1212883200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2008,6,8]]},"DOI":"10.1145\/1391469.1391700","type":"proceedings-article","created":{"date-parts":[[2008,7,30]],"date-time":"2008-07-30T12:09:58Z","timestamp":1217419798000},"page":"912-917","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":20,"title":["Leakage power reduction using stress-enhanced layouts"],"prefix":"10.1145","author":[{"given":"Vivek","family":"Joshi","sequence":"first","affiliation":[{"name":"University of Michigan, Ann Arbor, MI"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Brian","family":"Cline","sequence":"additional","affiliation":[{"name":"University of Michigan, Ann Arbor, MI"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dennis","family":"Sylvester","sequence":"additional","affiliation":[{"name":"University of Michigan, Ann Arbor, MI"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"David","family":"Blaauw","sequence":"additional","affiliation":[{"name":"University of Michigan, Ann Arbor, MI"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kanak","family":"Agarwal","sequence":"additional","affiliation":[{"name":"IBM Research, Austin, TX"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2008,6,8]]},"reference":[{"key":"e_1_3_2_1_1_1","first-page":"176","volume-title":"Proc. VLSI Tech. Symp. Tech. Dig.","author":"Andrieu F.","year":"2005","unstructured":"F. Andrieu in Proc. VLSI Tech. Symp. Tech. Dig. , pp. 176 -- 177 , 2005 . F. Andrieu et al., \"Experimental and Comparative Investigation of Low and High Field Transport in Substrate- and Process-Induced Strained Nanoscale MOSFETs,\" in Proc. VLSI Tech. Symp. Tech. Dig., pp. 176--177, 2005."},{"key":"e_1_3_2_1_2_1","first-page":"50","volume-title":"VLSI Technol. Symp. Tech. Dig.","author":"Mistry K.","year":"2005","unstructured":"K. Mistry : Uniaxial Strained Silicon Transistors in a 90nm CMOS Technology,\" in Proc . VLSI Technol. Symp. Tech. Dig. , pp. 50 -- 51 , 2005 . K. Mistry et al., \"Delaying Forever: Uniaxial Strained Silicon Transistors in a 90nm CMOS Technology,\" in Proc. VLSI Technol. Symp. Tech. Dig., pp. 50--51, 2005."},{"key":"e_1_3_2_1_3_1","unstructured":"S. Wolf \"Silicon Processing for the VLSI Era \" Lattice Press 1995.  S. Wolf \"Silicon Processing for the VLSI Era \" Lattice Press 1995."},{"key":"e_1_3_2_1_4_1","volume-title":"Design of High-Performance Microprocessor Circuits,\" in IEEE press","author":"Chandrakasan A.","year":"2001","unstructured":"A. Chandrakasan , \" Design of High-Performance Microprocessor Circuits,\" in IEEE press , 2001 . A. Chandrakasan et al., \"Design of High-Performance Microprocessor Circuits,\" in IEEE press, 2001."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.994980"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/277044.277179"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2006.889370"},{"key":"e_1_3_2_1_8_1","first-page":"117","volume-title":"IEDM","author":"Bianchi R. A.","year":"2002","unstructured":"R. A. Bianchi modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance,\" in Proc . IEDM , pp. 117 -- 120 , 2002 . R. A. Bianchi et al., \"Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance,\" in Proc. IEDM, pp. 117--120, 2002."},{"key":"e_1_3_2_1_9_1","volume-title":"Proc. ICCAD","author":"Kahng A.","year":"2007","unstructured":"A. Kahng STI Stress for Performance ,\" in Proc. ICCAD , November 2007 . A. Kahng et al., \"Exploiting STI Stress for Performance,\" in Proc. ICCAD, November 2007."},{"key":"e_1_3_2_1_10_1","first-page":"143","volume-title":"Proc. SISPAD","author":"Moroz V.","year":"2005","unstructured":"V. Moroz in Proc. SISPAD , pp. 143 -- 146 , 2005 . V. Moroz et al., \"The Impact of Layout on Stress-Enhanced Transistor Performance,\" in Proc. SISPAD, pp. 143--146, 2005."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2005.881001"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1353629.1353666"},{"key":"e_1_3_2_1_13_1","first-page":"667","volume-title":"Proc. CICC","author":"Chan V.","year":"2005","unstructured":"V. Chan PMOS performance Improvement ,\" in Proc. CICC , pp. 667 -- 674 , 2005 . V. Chan et al., \"Strain for PMOS performance Improvement,\" in Proc. CICC, pp. 667--674, 2005."},{"key":"e_1_3_2_1_14_1","volume-title":"IEDM","author":"Lee W. H.","year":"2005","unstructured":"W. H. Lee SOI technology with enhanced transistor strain and advanced-low-K BEOL,\" in Proc . IEDM , 2005 . W. H. Lee et al., \"High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL,\" in Proc. IEDM, 2005."},{"key":"e_1_3_2_1_15_1","first-page":"1075","volume-title":"IEDM","author":"Yang H. S.","year":"2004","unstructured":"H. S. Yang stress liner for high performance sub-45nm gate length SOI CMOS manufacturing,\" in Proc . IEDM , pp. 1075 -- 1077 , 2004 . H. S. Yang et al., \"Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing,\" in Proc. IEDM, pp. 1075--1077, 2004."},{"key":"e_1_3_2_1_16_1","first-page":"27","volume-title":"IEDM","author":"Ota K.","year":"2002","unstructured":"K. Ota locally strained channel technique for high performance 55nm CMOS,\" in Proc . IEDM , pp. 27 -- 30 , 2002 . K. Ota et al., \"Novel locally strained channel technique for high performance 55nm CMOS,\" in Proc. IEDM, pp. 27--30, 2002."},{"key":"e_1_3_2_1_17_1","first-page":"489","volume-title":"IEDM","author":"Luo Z.","year":"2005","unstructured":"Z. Luo of high performance PFETs with strained si channel and laser anneal,\" in Proc . IEDM , pp. 489 -- 492 , 2005 . Z. Luo et al., \"Design of high performance PFETs with strained si channel and laser anneal,\" in Proc. IEDM, pp. 489--492, 2005."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"crossref","unstructured":"Manual Davinci 3D TCAD Version 2005.10.  Manual Davinci 3D TCAD Version 2005.10.","DOI":"10.1016\/j.math.2005.06.005"},{"key":"e_1_3_2_1_19_1","first-page":"03","year":"2007","unstructured":"Manual, Synopsys TSUPREM4 , Version 2007 . 03 . Manual, Synopsys TSUPREM4, Version 2007.03.","journal-title":"Version"},{"key":"e_1_3_2_1_20_1","first-page":"143","volume-title":"ICCD","author":"Dharchoudhury A.","year":"1997","unstructured":"A. Dharchoudhury sizing and timing verification of domino circuits in the powerPC#8482; microprocessor,\" in Proc . ICCD , pp. 143 -- 148 , Oct. 1997 . A. Dharchoudhury et al., \"Transistor-level sizing and timing verification of domino circuits in the powerPC#8482; microprocessor,\" in Proc. ICCD, pp. 143--148, Oct. 1997."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/566408.566451"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278539"}],"event":{"name":"DAC '08: The 45th Annual Design Automation Conference 2008","sponsor":["The EDA Consortium","IEEE\/CASS\/CANDE\/CEDA","SIGDA ACM Special Interest Group on Design Automation"],"location":"Anaheim California","acronym":"DAC '08"},"container-title":["Proceedings of the 45th annual Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1391469.1391700","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1391469.1391700","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T14:47:13Z","timestamp":1750258033000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1391469.1391700"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,6,8]]},"references-count":22,"alternative-id":["10.1145\/1391469.1391700","10.1145\/1391469"],"URL":"https:\/\/doi.org\/10.1145\/1391469.1391700","relation":{},"subject":[],"published":{"date-parts":[[2008,6,8]]},"assertion":[{"value":"2008-06-08","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}