{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,4]],"date-time":"2026-10-04T01:34:16Z","timestamp":1791077656490,"version":"4.1.0"},"publisher-location":"New York, NY, USA","reference-count":22,"publisher":"ACM","license":[{"start":{"date-parts":[[2008,6,8]],"date-time":"2008-06-08T00:00:00Z","timestamp":1212883200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100006602","name":"Air Force Research Laboratory","doi-asserted-by":"publisher","award":["FA8750-05-1-0282"],"award-info":[{"award-number":["FA8750-05-1-0282"]}],"id":[{"id":"10.13039\/100006602","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000143","name":"Division of Computing and Communication Foundations","doi-asserted-by":"publisher","award":["CCF-0702276"],"award-info":[{"award-number":["CCF-0702276"]}],"id":[{"id":"10.13039\/100000143","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2008,6,8]]},"DOI":"10.1145\/1391469.1391703","type":"proceedings-article","created":{"date-parts":[[2008,7,30]],"date-time":"2008-07-30T12:09:58Z","timestamp":1217419798000},"page":"924-929","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":28,"title":["On the role of timing masking in reliable logic circuit design"],"prefix":"10.1145","author":[{"given":"Smita","family":"Krishnaswamy","sequence":"first","affiliation":[{"name":"The University of Michigan, Ann Arbor, MI"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Igor L.","family":"Markov","sequence":"additional","affiliation":[{"name":"The University of Michigan, Ann Arbor, MI and Synplicity Inc., Sunnyvale, CA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"John P.","family":"Hayes","sequence":"additional","affiliation":[{"name":"The University of Michigan, Ann Arbor, MI"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2008,6,8]]},"reference":[{"key":"e_1_3_2_1_1_1","first-page":"1","volume-title":"ITC","author":"S. Almukhaizim","year":"2006","unstructured":"S. Almukhaizim et al., \" Seamless Integration of SER in Rewiring-Based Design Space Exploration ,\" ITC 2006 , pp. 1 -- 9 . S. Almukhaizim et al., \"Seamless Integration of SER in Rewiring-Based Design Space Exploration,\" ITC 2006, pp. 1--9."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/332357.332377"},{"key":"e_1_3_2_1_3_1","first-page":"95","article-title":"Techniques for Fast Physical Synthesis","author":"Alpert C. J.","year":"2007","unstructured":"C. J. Alpert , , \" Techniques for Fast Physical Synthesis ,\" IEEE , March 2007 , vol. 95 , no. 3, pp. 573--599. C. J. Alpert, et al., \"Techniques for Fast Physical Synthesis,\" IEEE, March 2007, vol. 95, no. 3, pp. 573--599.","journal-title":"IEEE"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337549"},{"key":"e_1_3_2_1_5_1","first-page":"1454","article-title":"Accurate and Scalable Reliability Analysis of Logic Circuits","author":"Choudhury M.","year":"2007","unstructured":"M. Choudhury , K. Mohanram , \" Accurate and Scalable Reliability Analysis of Logic Circuits ,\" DATE 2007 , pp. 1454 -- 1459 . M. Choudhury, K. Mohanram, \"Accurate and Scalable Reliability Analysis of Logic Circuits,\" DATE 2007, pp. 1454--1459.","journal-title":"DATE"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1055137.1055145"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2004.85"},{"key":"e_1_3_2_1_8_1","unstructured":"IWLS 05 Benchmarks http:\/\/iwls.org\/iwls2005\/benchmarks.html  IWLS 05 Benchmarks http:\/\/iwls.org\/iwls2005\/benchmarks.html"},{"key":"e_1_3_2_1_9_1","first-page":"149","volume-title":"ICCAD 2007","author":"Krishnaswamy S.","unstructured":"S. Krishnaswamy , S. M. Plaza , I. L. Markov , J. P. Hayes , \" Enhancing Design Robustness with Reliability-aware Resynthesis and Logic Simulation ,\" ICCAD 2007 pp. 149 -- 154 . S. Krishnaswamy, S. M. Plaza, I. L. Markov, J. P. Hayes, \"Enhancing Design Robustness with Reliability-aware Resynthesis and Logic Simulation,\" ICCAD 2007 pp. 149--154."},{"key":"e_1_3_2_1_10_1","unstructured":"H. K. Lee D. S. Ha \"On the Generation of Test Patterns for Combinational Circuits \" TR No. 12--93 EE Dept. Virginia Polytechnic Institute.  H. K. Lee D. S. Ha \"On the Generation of Test Patterns for Combinational Circuits \" TR No. 12--93 EE Dept. Virginia Polytechnic Institute."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147104"},{"key":"e_1_3_2_1_12_1","first-page":"433","article-title":"Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits","author":"Mohanram K.","year":"2003","unstructured":"K. Mohanram , N. A. Touba , \" Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits \" DFT 2003 , pp. 433 -- 440 . K. Mohanram, N. A. Touba, \"Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits\" DFT 2003, pp. 433--440.","journal-title":"DFT"},{"key":"e_1_3_2_1_13_1","first-page":"86","volume-title":"VTS","author":"Nicolaidis M.","year":"1999","unstructured":"M. Nicolaidis , \" Time Redundancy Based Soft-Error Tolerant Circuits to Rescue Very Deep Submicron' ,\" VTS 1999 , pp. 86 -- 94 . M. Nicolaidis, \"Time Redundancy Based Soft-Error Tolerant Circuits to Rescue Very Deep Submicron',\" VTS 1999, pp. 86--94."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.358021"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233603"},{"key":"e_1_3_2_1_16_1","first-page":"164","article-title":"An Efficient Static Algorithm for Computing the Soft Error Rates of Combinational Circuits","author":"Rao R.","year":"2006","unstructured":"R. Rao , , \" An Efficient Static Algorithm for Computing the Soft Error Rates of Combinational Circuits ,\" DATE 2006 , pp. 164 -- 169 . R. Rao, et al., \"An Efficient Static Algorithm for Computing the Soft Error Rates of Combinational Circuits,\" DATE 2006, pp. 164--169.","journal-title":"DATE"},{"key":"e_1_3_2_1_17_1","first-page":"389","volume-title":"DSN","author":"Shivakumar P.","year":"2002","unstructured":"P. Shivakumar , Modeling the Effect of Technology Trends on Soft Error Rate of Combinational Logic\" DSN 2002 , pp. 389 -- 398 . P. Shivakumar, et al., \"Modeling the Effect of Technology Trends on Soft Error Rate of Combinational Logic\" DSN 2002, pp. 389--398."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"crossref","unstructured":"J. von Neumann \"Probabilistic Logics & Synthesis of Reliable Organisms from Unreliable Components \" Automata Studies 1956.  J. von Neumann \"Probabilistic Logics & Synthesis of Reliable Organisms from Unreliable Components \" Automata Studies 1956.","DOI":"10.1515\/9781400882618-003"},{"key":"e_1_3_2_1_19_1","unstructured":"UMICH Physical Design Tools http:\/\/vlsicad.eecs.umich.edu\/BK\/PDtools\/  UMICH Physical Design Tools http:\/\/vlsicad.eecs.umich.edu\/BK\/PDtools\/"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.64"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382553"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.853696"}],"event":{"name":"DAC '08: The 45th Annual Design Automation Conference 2008","location":"Anaheim California","acronym":"DAC '08","sponsor":["The EDA Consortium","IEEE\/CASS\/CANDE\/CEDA","SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the 45th annual Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1391469.1391703","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1391469.1391703","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T14:47:13Z","timestamp":1750258033000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1391469.1391703"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,6,8]]},"references-count":22,"alternative-id":["10.1145\/1391469.1391703","10.1145\/1391469"],"URL":"https:\/\/doi.org\/10.1145\/1391469.1391703","relation":{},"subject":[],"published":{"date-parts":[[2008,6,8]]},"assertion":[{"value":"2008-06-08","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}