{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:58:58Z","timestamp":1759147138998,"version":"3.41.0"},"reference-count":21,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2008,9,1]],"date-time":"2008-09-01T00:00:00Z","timestamp":1220227200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2008,9]]},"abstract":"<jats:p>FPGA clock networks consume a significant amount of power, since they toggle every clock cycle and must be flexible enough to implement the clocks for a wide range of different applications. The efficiency of FPGA clock networks can be improved by reducing this flexibility; however, reducing the flexibility introduces stricter constraints during the clustering and placement stages of the FPGA CAD flow. These constraints can reduce the overall efficiency of the final implementation. This article examines the trade-off between the power consumption and flexibility of FPGA clock networks.<\/jats:p>\n          <jats:p>Specifically, this article makes three contributions. First, it presents a new parameterized clock-network framework for describing and comparing FPGA clock networks. Second, it describes new clock-aware placement techniques that are needed to find a legal placement satisfying the constraints imposed by the clock network. Finally, it performs an empirical study to examine the trade-off between the power consumption of the clock network and the impact of the CAD constraints for a number of different clock networks with varying amounts of flexibility.<\/jats:p>\n          <jats:p>The results show that the techniques used to produce a legal placement can have a significant influence on power and the ability of the placer to find a legal solution. On average, circuits placed using the most effective techniques dissipate 5% less overall energy and are significantly more likely to be legal than circuits placed using other techniques. Moreover, the results show that the architecture of the clock network is also important. On average, FPGAs with an efficient clock network are up to 14.6% more energy efficient compared to other FPGAs.<\/jats:p>","DOI":"10.1145\/1391732.1391733","type":"journal-article","created":{"date-parts":[[2009,1,13]],"date-time":"2009-01-13T13:15:48Z","timestamp":1231852548000},"page":"1-33","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":7,"title":["On the trade-off between power and flexibility of FPGA clock networks"],"prefix":"10.1145","volume":"1","author":[{"given":"Julien","family":"Lamoureux","sequence":"first","affiliation":[{"name":"University of British Columbia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Steven J. E.","family":"Wilton","sequence":"additional","affiliation":[{"name":"University of British Columbia"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2008,9,19]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"ACTEL. 2007. ProASIC3 flash family FPGAs datasheet: Device architecture (Jan.).  ACTEL. 2007. ProASIC3 flash family FPGAs datasheet: Device architecture (Jan.)."},{"key":"e_1_2_1_2_1","unstructured":"ALTERA. 2005. Stratix II Device Handbook 1. Chapter 2 (Mar.).  ALTERA. 2005. Stratix II Device Handbook 1. Chapter 2 (Mar.)."},{"key":"e_1_2_1_3_1","unstructured":"ALTERA. 2006. Stratix III Device Handbook 1. Chapter 6 (Nov.).  ALTERA. 2006. Stratix III Device Handbook 1. Chapter 6 (Nov.)."},{"volume-title":"Circuits, Interconnections, and","author":"Bakolgu H. B.","key":"e_1_2_1_4_1"},{"key":"e_1_2_1_5_1","doi-asserted-by":"crossref","unstructured":"Betz V. Rose J. and Marquardt A. 1999. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic.   Betz V. Rose J. and Marquardt A. 1999. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic.","DOI":"10.1007\/978-1-4615-5145-4"},{"volume-title":"Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), 139--142","author":"Brynjolfson I.","key":"e_1_2_1_6_1"},{"volume-title":"Proceedings of the Great Lakes Symposium on VLSI, 143--147","author":"Edahiro M.","key":"e_1_2_1_7_1"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.929649"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/313817.313920"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1166\/jolpe.2005.023"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1117201.1117216"},{"volume-title":"Proceedings of the International Conference on Field-Programmable Logic and Applications (FPL).","author":"Lamoureux J.","key":"e_1_2_1_12_1"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1971.223159"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/611817.611844"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1982.1675941"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1059876.1059881"},{"volume-title":"Proceedings of the International Conference on VLSI Design, 146--149","author":"Natesan V.","key":"e_1_2_1_17_1"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/611817.611838"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1117201.1117203"},{"key":"e_1_2_1_20_1","unstructured":"XILINX. 2007. Virtex-5 User Guide. Chapter 2 (Feb).  XILINX. 2007. Virtex-5 User Guide. Chapter 2 (Feb)."},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.602474"}],"container-title":["ACM Transactions on Reconfigurable Technology and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1391732.1391733","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1391732.1391733","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T14:47:13Z","timestamp":1750258033000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1391732.1391733"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,9]]},"references-count":21,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2008,9]]}},"alternative-id":["10.1145\/1391732.1391733"],"URL":"https:\/\/doi.org\/10.1145\/1391732.1391733","relation":{},"ISSN":["1936-7406","1936-7414"],"issn-type":[{"type":"print","value":"1936-7406"},{"type":"electronic","value":"1936-7414"}],"subject":[],"published":{"date-parts":[[2008,9]]},"assertion":[{"value":"2007-07-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2008-04-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2008-09-19","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}