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Runtime reconfigurable hardware can provide this flexibility but the reconfiguration latency can significantly decrease the performance. When dealing with task graphs, runtime support that schedules the reconfigurations in advance can drastically reduce this overhead. However, executing complex scheduling heuristics at runtime may generate an excessive penalty. Hence, we have developed a hybrid design-time\/runtime reconfiguration scheduling heuristic that generates its final schedule at runtime but carries out most computations at design-time. We have tested our approach in a PowerPC 405 processor embedded on a FPGA demonstrating that it generates a very small runtime penalty while providing almost as good schedules as a full runtime approach.<\/jats:p>","DOI":"10.1145\/1391962.1391966","type":"journal-article","created":{"date-parts":[[2008,10,7]],"date-time":"2008-10-07T12:48:29Z","timestamp":1223383709000},"page":"1-12","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":18,"title":["Efficiently scheduling runtime reconfigurations"],"prefix":"10.1145","volume":"13","author":[{"given":"Javier","family":"Resano","sequence":"first","affiliation":[{"name":"Universidad Complutense de Madrid, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Juan Antonio","family":"Clemente","sequence":"additional","affiliation":[{"name":"Universidad Complutense de Madrid, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Carlos","family":"Gonzalez","sequence":"additional","affiliation":[{"name":"Universidad Complutense de Madrid, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Daniel","family":"Mozos","sequence":"additional","affiliation":[{"name":"Universidad Complutense de Madrid, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Francky","family":"Catthoor","sequence":"additional","affiliation":[{"name":"IMEC vzw and Katholieke Universiteit Leuven, Heverlee, Belgium"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2008,10,3]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1147\/sj.52.0078"},{"key":"e_1_2_1_2_1","unstructured":"EDK. 2007. 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Lysaght, P., Blodget, B., Mason, J., Young, J., and Bridgford B. 2006. Enhanced architectures, design methodologies and CAD tools for dynamic reconfiguration of Xilinx FPGAs. In Proceedings of the 2006 International Conference on Field Programmable Logic and Applications. Madrid, Spain, 1--6."},{"volume-title":"Proceedings of the 12th International Conference on Field-Programmable Logic and Applications","author":"Marescaux T.","key":"e_1_2_1_6_1","unstructured":"Marescaux , T. , Bartic , A. , Verkest , D. , Vernalde , S. , and Lauwereins , R . 2002. Interconnection networks enable fine-grain dynamic multi-tasking FPGAs . In Proceedings of the 12th International Conference on Field-Programmable Logic and Applications . Montpellier, France, 795--805. Marescaux, T., Bartic, A., Verkest, D., Vernalde, S., and Lauwereins, R. 2002. Interconnection networks enable fine-grain dynamic multi-tasking FPGAs. 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Hardware-software co-synthesis of low power real-time distributed embedded systems with dynamically reconfigurable FPGAs. In Proceedings of the Conference on Asia South Pacific Design Automation\/VLSI Design, Bangalore, India, 345--360."},{"volume-title":"Proceedings of the 14th International Conference on Field-Programmable Logic and Applications","author":"Walder H.","key":"e_1_2_1_16_1","unstructured":"Walder , H. and Platzner , M . 2004. A runtime environment for reconfigurable operating systems . In Proceedings of the 14th International Conference on Field-Programmable Logic and Applications , Leuven, Belgium, 831--835. Walder, H. and Platzner, M. 2004. A runtime environment for reconfigurable operating systems. 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