{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:37:19Z","timestamp":1750307839807,"version":"3.41.0"},"reference-count":24,"publisher":"Association for Computing Machinery (ACM)","issue":"5","license":[{"start":{"date-parts":[[2008,5,1]],"date-time":"2008-05-01T00:00:00Z","timestamp":1209600000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGPLAN Not."],"published-print":{"date-parts":[[2008,5]]},"abstract":"<jats:p>\n            As memory transactions have been proposed as a language-level replacement for locks, there is growing need for well-defined semantics. In contrast to database transactions, transaction memory (TM) semantics are complicated by the fact that programs may access the same memory locations both inside and outside transactions.\n            <jats:italic>Strongly atomic<\/jats:italic>\n            semantics, where non-transactional accesses are treated as implicit single-operation transactions, remain difficult to provide without specialized hardware support and\/or significant performance overhead. As an alternative, many in the community have informally proposed that a\n            <jats:italic>single global lock semantics<\/jats:italic>\n            [16, 9], where transaction semantics are mapped to those of regions protected by a single global lock, provide an intuitive and efficiently implementable model for programmers.\n          <\/jats:p>\n          <jats:p>In this paper, we explore the implementation and performance implications of single global lock semantics in a weakly atomic STM from the perspective of Java, and we discuss why even recent STM implementations fall short of these semantics. We describe a new weakly atomic Java STM implementation that provides single global lock semantics while permitting concurrent execution, but we show that this comes at a significant performance cost. We also propose and implement various alternative semantics that loosen single lock requirements while still providing strong guarantees. We compare our new implementations to previous ones, including a strongly atomic STM. [22]<\/jats:p>","DOI":"10.1145\/1402227.1402235","type":"journal-article","created":{"date-parts":[[2008,8,19]],"date-time":"2008-08-19T12:12:08Z","timestamp":1219147928000},"page":"15-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":23,"title":["Single global lock semantics in a weakly atomic STM"],"prefix":"10.1145","volume":"43","author":[{"given":"Vijay","family":"Menon","sequence":"first","affiliation":[{"name":"Intel Labs, Santa Clara, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Steven","family":"Balensiefer","sequence":"additional","affiliation":[{"name":"University of Washington, Seattle, WA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tatiana","family":"Shpeisman","sequence":"additional","affiliation":[{"name":"Intel Labs, Santa Clara, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ali-Reza","family":"Adl-Tabatabai","sequence":"additional","affiliation":[{"name":"Intel Labs, Santa Clara, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Richard L.","family":"Hudson","sequence":"additional","affiliation":[{"name":"Intel Labs, Santa Clara, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bratin","family":"Saha","sequence":"additional","affiliation":[{"name":"Intel Labs, Santa Clara, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Adam","family":"Welc","sequence":"additional","affiliation":[{"name":"Intel Labs, Santa Clara, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2008,5]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1328438.1328449"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1133981.1133985"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.546611"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.41"},{"key":"e_1_2_1_5_1","volume-title":"Fourth Annual Workshop on Duplicating, Deconstructing, and Debunking","author":"Blundell C.","year":"2005","unstructured":"C. Blundell , E. C. Lewis , and M. M. K. Martin . Deconstructing transactions : The subtleties of atomicity . In Fourth Annual Workshop on Duplicating, Deconstructing, and Debunking , 2005 . C. Blundell, E. C. Lewis, and M. M. K. Martin. Deconstructing transactions: The subtleties of atomicity. In Fourth Annual Workshop on Duplicating, Deconstructing, and Debunking, 2005."},{"key":"e_1_2_1_6_1","volume-title":"C++ standards committee paper WG21\/N1942","author":"Boehm H.","year":"2006","unstructured":"H. Boehm . A memory model for c++: Strawman proposal . In C++ standards committee paper WG21\/N1942 , February 2006 . http:\/\/www.open-std.org\/jtc1\/sc22\/wg21\/docs\/papers\/2006\/n1942.html. H. Boehm. A memory model for c++: Strawman proposal. In C++ standards committee paper WG21\/N1942, February 2006. http:\/\/www.open-std.org\/jtc1\/sc22\/wg21\/docs\/papers\/2006\/n1942.html."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1007\/11864219_14"},{"key":"e_1_2_1_8_1","volume-title":"Morgan Kaufmann","author":"Gray J.","year":"1993","unstructured":"J. Gray and A. Reuter . Transaction Processing: Concepts and Techniques . Morgan Kaufmann , 1993 . J. Gray and A. Reuter. Transaction Processing: Concepts and Techniques. Morgan Kaufmann, 1993."},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1178597.1178609"},{"key":"e_1_2_1_10_1","volume-title":"ISCA","author":"Hammond L.","year":"2004","unstructured":"L. Hammond , V. Wong , M. Chen , B. D. Carlstrom , J. D. Davis , B. Hertzberg , M. K. Prabhu , H. Wijaya , C. Kozyrakis , and K. Olukotun . Transactional memory coherence and consistency . In ISCA 2004 . L. Hammond, V. Wong, M. Chen, B. D. Carlstrom, J. D. Davis, B. Hertzberg, M. K. Prabhu, H. Wijaya, C. Kozyrakis, and K. Olukotun. Transactional memory coherence and consistency. In ISCA 2004."},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/949305.949340"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065944.1065952"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1133981.1133984"},{"key":"e_1_2_1_14_1","unstructured":"Intel Corporation. Intel 64 Architecture Memory Ordering White Paper. http:\/\/www.intel.com\/products\/processor\/manuals\/318147.pdf.  Intel Corporation. Intel 64 Architecture Memory Ordering White Paper. http:\/\/www.intel.com\/products\/processor\/manuals\/318147.pdf."},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1979.1675439"},{"key":"e_1_2_1_16_1","volume-title":"Transactional Memory. Morgan &amp","author":"Larus J.","year":"2006","unstructured":"J. Larus and R. Rajwar . Transactional Memory. Morgan &amp ; Claypool Publishers , 2006 . J. Larus and R. Rajwar. Transactional Memory. Morgan &amp; Claypool Publishers, 2006."},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1040305.1040336"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2006.1598134"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1328438.1328448"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.54"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250734.1250744"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/1281100.1281161"},{"key":"e_1_2_1_25_1","unstructured":"H. Sutter. Prism - A Principle-Based Sequential Memory Model for Microsoft Native Code Platforms Draft Version 0.9.1. http:\/\/www.open-std.org\/jtc1\/sc22\/wg21\/docs\/papers\/2006\/n2075.pdf September 2006.  H. Sutter. Prism - A Principle-Based Sequential Memory Model for Microsoft Native Code Platforms Draft Version 0.9.1. http:\/\/www.open-std.org\/jtc1\/sc22\/wg21\/docs\/papers\/2006\/n2075.pdf September 2006."},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2007.4"}],"container-title":["ACM SIGPLAN Notices"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1402227.1402235","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1402227.1402235","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:58:05Z","timestamp":1750255085000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1402227.1402235"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,5]]},"references-count":24,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2008,5]]}},"alternative-id":["10.1145\/1402227.1402235"],"URL":"https:\/\/doi.org\/10.1145\/1402227.1402235","relation":{},"ISSN":["0362-1340","1558-1160"],"issn-type":[{"type":"print","value":"0362-1340"},{"type":"electronic","value":"1558-1160"}],"subject":[],"published":{"date-parts":[[2008,5]]},"assertion":[{"value":"2008-05-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}