{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:34:31Z","timestamp":1750307671655,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":13,"publisher":"ACM","license":[{"start":{"date-parts":[[2008,9,1]],"date-time":"2008-09-01T00:00:00Z","timestamp":1220227200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2008,9]]},"DOI":"10.1145\/1404371.1404389","type":"proceedings-article","created":{"date-parts":[[2008,9,4]],"date-time":"2008-09-04T21:44:44Z","timestamp":1220564684000},"page":"28-33","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["A new march sequence to fit DDR SDRAM test in burst mode"],"prefix":"10.1145","author":[{"given":"Andr\u00e9 Borin","family":"Soares","sequence":"first","affiliation":[{"name":"Universidade Federal do Rio Grande do Sul - UFRGS, Porto Alegre, Brazil"}]},{"given":"Alexsandro Cristov\u00e3o","family":"Bonatto","sequence":"additional","affiliation":[{"name":"Universidade Federal do Rio Grande do Sul - UFRGS, Porto Alegre, Brazil"}]},{"given":"Altamiro Amadeu","family":"Susin","sequence":"additional","affiliation":[{"name":"Universidade Federal do Rio Grande do Sul - UFRGS, Porto Alegre, Brazil"}]}],"member":"320","published-online":{"date-parts":[[2008,9]]},"reference":[{"key":"e_1_3_2_1_1_1","first-page":"177","volume-title":"DDR SDRAM Memory Controller Validation for FPGA Synthesis. In LATW2008: Proceedings of the 9th IEEE Latin-American Test Workshop","author":"Bonatto A.","year":"2008","unstructured":"A. Bonatto , A. Borin , and A. Susin . DDR SDRAM Memory Controller Validation for FPGA Synthesis. In LATW2008: Proceedings of the 9th IEEE Latin-American Test Workshop , pages 177 -- 182 , Puebla, Mexico , Feb. 2008 . A. Bonatto, A. Borin, and A. Susin. DDR SDRAM Memory Controller Validation for FPGA Synthesis. In LATW2008: Proceedings of the 9th IEEE Latin-American Test Workshop, pages 177--182, Puebla, Mexico, Feb. 2008."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"crossref","DOI":"10.1007\/b117406","volume-title":"Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits, page 690","author":"Bushnell M. L.","year":"2002","unstructured":"M. L. Bushnell and V. D. Agrawal . Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits, page 690 . Kluwer Academic , Secaucus, NJ, USA , 2002 . M. L. Bushnell and V. D. Agrawal. Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits, page 690. Kluwer Academic, Secaucus, NJ, USA, 2002."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1271204"},{"key":"e_1_3_2_1_4_1","volume-title":"JESD79: Double Data Rate (DDR) SDRAM Specification","author":"JEDEC.","year":"2003","unstructured":"JEDEC. JESD79: Double Data Rate (DDR) SDRAM Specification . JEDEC Solid State Technology Association , Virginia, USA , 2003 . JEDEC. JESD79: Double Data Rate (DDR) SDRAM Specification. JEDEC Solid State Technology Association, Virginia, USA, 2003."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.5555\/1116164.1116464"},{"key":"e_1_3_2_1_6_1","unstructured":"Micron. Micron DDR SDRAM Products. {Online} Available: http:\/\/www.micron.com\/products\/dram\/ddr\/.  Micron. Micron DDR SDRAM Products. {Online} Available: http:\/\/www.micron.com\/products\/dram\/ddr\/."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/MTDT.2005.9"},{"key":"e_1_3_2_1_8_1","first-page":"944","volume-title":"Minimal Test for Coupling Faults in Word-Oriented Memories. In DATE '02: Proceedings of the conference on Design, automation and test in Europe","author":"van de Goor A.","year":"2002","unstructured":"A. van de Goor , M. Abadir , and A. Carlin . Minimal Test for Coupling Faults in Word-Oriented Memories. In DATE '02: Proceedings of the conference on Design, automation and test in Europe , page 944 , Washington, DC, USA , 2002 . IEEE Computer Society. A. van de Goor, M. Abadir, and A. Carlin. Minimal Test for Coupling Faults in Word-Oriented Memories. In DATE '02: Proceedings of the conference on Design, automation and test in Europe, page 944, Washington, DC, USA, 2002. IEEE Computer Society."},{"key":"e_1_3_2_1_9_1","volume-title":"Testing semiconductor memories: theory and practice","author":"van de Goor A. J.","year":"1991","unstructured":"A. J. van de Goor . Testing semiconductor memories: theory and practice . John Wiley & amp; Sons, Inc., New York, NY, USA, 1991 . A. J. van de Goor. Testing semiconductor memories: theory and practice. John Wiley & Sons, Inc., New York, NY, USA, 1991."},{"key":"e_1_3_2_1_10_1","first-page":"13","volume-title":"An Analysis of (Linked) Address Decoder Faults. In MTDT '97: Proceedings of the 1997 IEEE International Workshop on Memory Technology, Design and Testing","author":"van de Goor A. J.","year":"1997","unstructured":"A. J. van de Goor and G. N. Gaydadjiev . An Analysis of (Linked) Address Decoder Faults. In MTDT '97: Proceedings of the 1997 IEEE International Workshop on Memory Technology, Design and Testing , page 13 , Washington, DC, USA , 1997 . IEEE Computer Society. A. J. van de Goor and G. N. Gaydadjiev. An Analysis of (Linked) Address Decoder Faults. In MTDT '97: Proceedings of the 1997 IEEE International Workshop on Memory Technology, Design and Testing, page 13, Washington, DC, USA, 1997. IEEE Computer Society."},{"key":"e_1_3_2_1_11_1","first-page":"501","volume-title":"Tlili. March Tests for Word-Oriented Memories. In DATE '98: Proceedings of the conference on Design, automation and test in Europe","author":"van de Goor A. J.","year":"1998","unstructured":"A. J. van de Goor and I. B. S. Tlili. March Tests for Word-Oriented Memories. In DATE '98: Proceedings of the conference on Design, automation and test in Europe , pages 501 -- 509 , Washington, DC, USA , 1998 . IEEE Computer Society. A. J. van de Goor and I. B. S. Tlili. March Tests for Word-Oriented Memories. In DATE '98: Proceedings of the conference on Design, automation and test in Europe, pages 501--509, Washington, DC, USA, 1998. IEEE Computer Society."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2003.1173052"},{"key":"e_1_3_2_1_13_1","unstructured":"Xilinx. Xilinx Memory Solutions. {Online} Available: http:\/\/www.xilinx.com\/memory.  Xilinx. Xilinx Memory Solutions. {Online} Available: http:\/\/www.xilinx.com\/memory."}],"event":{"name":"SBCCI08: 21st Symposium on Integrated Circuits and System Design","sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"],"location":"Gramado Brazil","acronym":"SBCCI08"},"container-title":["Proceedings of the 21st annual symposium on Integrated circuits and system design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1404371.1404389","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1404371.1404389","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:29:38Z","timestamp":1750253378000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1404371.1404389"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,9]]},"references-count":13,"alternative-id":["10.1145\/1404371.1404389","10.1145\/1404371"],"URL":"https:\/\/doi.org\/10.1145\/1404371.1404389","relation":{},"subject":[],"published":{"date-parts":[[2008,9]]},"assertion":[{"value":"2008-09-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}