{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:58:30Z","timestamp":1750309110689,"version":"3.41.0"},"reference-count":20,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2008,10,1]],"date-time":"2008-10-01T00:00:00Z","timestamp":1222819200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2008,10]]},"abstract":"<jats:p>With aggressive reductions in feature sizes and the integration of multiple functionalities on the same die, bottlenecks due to I\/O pin limitations have become a critical issue in today's VLSI designs, especially for 3D IC technologies. To alleviate the pin limitation problem, a stacked-Vdd circuit paradigm has recently been proposed in the literature. However, for a circuit designed using this paradigm, a significant amount of power may be wasted if modules are not carefully assigned to different Vdd domains. In this article, we present a partition-based algorithm for efficiently assigning modules at the floorplanning level, so as to reuse currents between Vdd domains and minimize the power wasted during the operation of the circuit. Experimental results on both 3D and 2D ICs show that compared with assigning modules to different Vdd domains using enumeration and simulated annealing, our algorithm can generate circuits with competitive power and IR noise performance, while being orders of magnitude faster.<\/jats:p>","DOI":"10.1145\/1412587.1412591","type":"journal-article","created":{"date-parts":[[2008,11,6]],"date-time":"2008-11-06T13:49:43Z","timestamp":1225979383000},"page":"1-20","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["Automated module assignment in stacked-Vdd designs for high-efficiency power delivery"],"prefix":"10.1145","volume":"4","author":[{"given":"Yong","family":"Zhan","sequence":"first","affiliation":[{"name":"Cadence Design Systems, San Jose, CA"}]},{"given":"Sachin S.","family":"Sapatnekar","sequence":"additional","affiliation":[{"name":"University of Minnesota, Minneapolis, MN"}]}],"member":"320","published-online":{"date-parts":[[2008,11,7]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.817546"},{"key":"e_1_2_1_2_1","unstructured":"Austin T. and Burger D. 2008. Simplescalar tutorial. http:\/\/www.simplescalar.com\/docs\/simple_tutorial_v2.pdf.  Austin T. and Burger D. 2008. Simplescalar tutorial. http:\/\/www.simplescalar.com\/docs\/simple_tutorial_v2.pdf."},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.929647"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382626"},{"volume-title":"Proceedings of the IEEE Asia and South Pacific Design Automation Conference, 780--785","author":"Cong J.","key":"e_1_2_1_5_1","unstructured":"Cong , J. , Luo , G. , Wei , J. , and Zhang , Y . 2007. Thermal-Aware 3D IC placement via transformation . In Proceedings of the IEEE Asia and South Pacific Design Automation Conference, 780--785 . Cong, J., Luo, G., Wei, J., and Zhang, Y. 2007. Thermal-Aware 3D IC placement via transformation. In Proceedings of the IEEE Asia and South Pacific Design Automation Conference, 780--785."},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382591"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.136"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.5555\/996070.1009873"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.870069"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278637"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1077603.1077651"},{"volume-title":"Complexity of Computer Computations","author":"Karp R. M.","key":"e_1_2_1_12_1","unstructured":"Karp , R. M. 1972. Reducibility among combinatorial problems . In R. E. Miller and J. W. Thatcher, eds. Complexity of Computer Computations . Plenum , New York , 85--103. Karp, R. M. 1972. Reducibility among combinatorial problems. In R. E. Miller and J. W. Thatcher, eds. Complexity of Computer Computations. Plenum, New York, 85--103."},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.858276"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1165573.1165644"},{"volume-title":"Proceedings of the IEEE International Solid-State Circuits Conference, 298--299","author":"Rajapandian S.","key":"e_1_2_1_15_1","unstructured":"Rajapandian , S. , Shepard , K. , Hazucha , P. , and Karnik , T . 2005. High-Tension power delivery: Operating 0.18&mu;m CMOS digital logic at 5.4V. In Digest of Technical Papers , Proceedings of the IEEE International Solid-State Circuits Conference, 298--299 . Rajapandian, S., Shepard, K., Hazucha, P., and Karnik, T. 2005. High-Tension power delivery: Operating 0.18&mu;m CMOS digital logic at 5.4V. In Digest of Technical Papers, Proceedings of the IEEE International Solid-State Circuits Conference, 298--299."},{"key":"e_1_2_1_16_1","unstructured":"Sait S. M. and Youssef H. 1995. VLSI Physical Design Automation: Theory and Practice. IEEE Press Piscataway NJ.   Sait S. M. and Youssef H. 1995. VLSI Physical Design Automation: Theory and Practice. IEEE Press Piscataway NJ."},{"key":"e_1_2_1_17_1","unstructured":"Semiconductor Industry Association. 2006. International technology roadmap for semiconductors. http:\/\/public.itrs.net\/Links\/2006Update\/2006UpdateFinal.htm.  Semiconductor Industry Association. 2006. International technology roadmap for semiconductors. http:\/\/public.itrs.net\/Links\/2006Update\/2006UpdateFinal.htm."},{"key":"e_1_2_1_18_1","first-page":"8","article-title":"Temperature-Aware placement for SOCs","volume":"94","author":"Tsai J. L.","year":"2006","unstructured":"Tsai , J. L. , Chen , C. C. P. , Chen , G. , Goplen , B. , Qian , H. , Zhan , Y. , Kang , S. M. , Wong , M. D. F. , and Sapatnekar , S. S. 2006 . Temperature-Aware placement for SOCs . Proc. IEEE 94 , 8 (Aug.), 1502--1518. Tsai, J. L., Chen, C. C. P., Chen, G., Goplen, B., Qian, H., Zhan, Y., Kang, S. M., Wong, M. D. F., and Sapatnekar, S. S. 2006. Temperature-Aware placement for SOCs. Proc. IEEE 94, 8 (Aug.), 1502--1518.","journal-title":"Proc. IEEE"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859629"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.895754"}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1412587.1412591","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1412587.1412591","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T22:48:51Z","timestamp":1750286931000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1412587.1412591"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,10]]},"references-count":20,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2008,10]]}},"alternative-id":["10.1145\/1412587.1412591"],"URL":"https:\/\/doi.org\/10.1145\/1412587.1412591","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"type":"print","value":"1550-4832"},{"type":"electronic","value":"1550-4840"}],"subject":[],"published":{"date-parts":[[2008,10]]},"assertion":[{"value":"2007-11-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2008-05-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2008-11-07","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}