{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:51:22Z","timestamp":1759146682685,"version":"3.41.0"},"reference-count":11,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2008,10,1]],"date-time":"2008-10-01T00:00:00Z","timestamp":1222819200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2008,10]]},"abstract":"<jats:p>We have developed a new three-dimensional stacking technology using the wafer-to-wafer stacked method. Electrical conductivity between each wafer is almost 100% and contact resistance is less than 0.7\u03a9 between a through-silicon via (TSV) and a microbump. We have also created a prototype of a three-layer stacking device using our technology, where each wafer for the stacking is fabricated by using 0.18um CMOS technology based on 8-inch wafers. The device is operated by two times the frequency of the multichip module (MCM) device case using a two-dimensional device with identical functions and minimally different power consumption. The yields obtained from the results comprising all functional tests are over 60%.<\/jats:p>","DOI":"10.1145\/1412587.1412593","type":"journal-article","created":{"date-parts":[[2008,11,6]],"date-time":"2008-11-06T13:49:43Z","timestamp":1225979383000},"page":"1-15","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":20,"title":["Multilayer stacking technology using wafer-to-wafer stacked method"],"prefix":"10.1145","volume":"4","author":[{"given":"Nobuaki","family":"Miyakawa","sequence":"first","affiliation":[{"name":"Honda Research Institute Japan, Saitama, Japan"}]},{"given":"Eiri","family":"Hashimoto","sequence":"additional","affiliation":[{"name":"Honda Research Institute Japan, Saitama, Japan"}]},{"given":"Takanori","family":"Maebashi","sequence":"additional","affiliation":[{"name":"Honda Research Institute Japan, Saitama, Japan"}]},{"given":"Natsuo","family":"Nakamura","sequence":"additional","affiliation":[{"name":"Honda Research Institute Japan, Saitama, Japan"}]},{"given":"Yutaka","family":"Sacho","sequence":"additional","affiliation":[{"name":"Honda Research Institute Japan, Saitama, Japan"}]},{"given":"Shigeto","family":"Nakayama","sequence":"additional","affiliation":[{"name":"Honda Research Institute Japan, Saitama, Japan"}]},{"given":"Shinjiro","family":"Toyoda","sequence":"additional","affiliation":[{"name":"Honda Research Institute Japan, Saitama, Japan"}]}],"member":"320","published-online":{"date-parts":[[2008,11,7]]},"reference":[{"volume-title":"IEEE International Electronic Devices Meeting Conference Digest Technology Papers, 359--362","author":"Fukushima T.","key":"e_1_2_1_1_1","unstructured":"Fukushima , T. , Yamada , Y. , Kikuchi , H. , and Koyanagi , M . 2005. New three-dimensional integration technology using self-assembly technique . In IEEE International Electronic Devices Meeting Conference Digest Technology Papers, 359--362 . Fukushima, T., Yamada, Y., Kikuchi, H., and Koyanagi, M. 2005. New three-dimensional integration technology using self-assembly technique. In IEEE International Electronic Devices Meeting Conference Digest Technology Papers, 359--362."},{"key":"e_1_2_1_2_1","unstructured":"ISSCC. 2007. ISSCC Forum on the Design of 3D-Chipstacks. ISSCC. 2007. ISSCC Forum on the Design of 3D-Chipstacks."},{"key":"e_1_2_1_3_1","doi-asserted-by":"crossref","unstructured":"Iwata A. Sasaki M. Kikkawa T. Kameda S. Ando H. Kimoto D. Arizono D. and Sunami H. 2005. A 3D integration scheme utilizing wireless interconnections for implementing hyper brains. ISSCC Dig. Tech. Papers 262--263. Iwata A. Sasaki M. Kikkawa T. Kameda S. Ando H. Kimoto D. Arizono D. and Sunami H. 2005. A 3D integration scheme utilizing wireless interconnections for implementing hyper brains. ISSCC Dig. Tech. Papers 262--263.","DOI":"10.1109\/ISSCC.2005.1493969"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.710867"},{"key":"e_1_2_1_5_1","doi-asserted-by":"crossref","unstructured":"Maebashi T. Nakamura N. Nakayama N. and Miyakawa N. 2007. New fabrication method for multi-layer stacked devices using wafer-to-wafer stacked technology based on 8-inch wafers.ESSDERC 251--254. Maebashi T. Nakamura N. Nakayama N. and Miyakawa N. 2007. New fabrication method for multi-layer stacked devices using wafer-to-wafer stacked technology based on 8-inch wafers.ESSDERC 251--254.","DOI":"10.1109\/ESSDERC.2007.4430925"},{"key":"e_1_2_1_6_1","first-page":"5","article-title":"Three-Dimensional wafer stacking via Cu-Cu bonding integrated with 65-nm strained-Si\/Low-k","volume":"27","author":"Morrow P. R.","year":"2006","unstructured":"Morrow , P. R. , Park , C.-M. , Ramanathan , S. , Kobrisksy , M. J. , and Harmes , M. 2006 . Three-Dimensional wafer stacking via Cu-Cu bonding integrated with 65-nm strained-Si\/Low-k . IEEE Electron. Devices 27 , 5 (May). Morrow, P. R., Park, C.-M., Ramanathan, S., Kobrisksy, M. J., and Harmes, M. 2006. Three-Dimensional wafer stacking via Cu-Cu bonding integrated with 65-nm strained-Si\/Low-k. IEEE Electron. Devices 27, 5 (May).","journal-title":"IEEE Electron. Devices"},{"key":"e_1_2_1_7_1","volume-title":"Proceedings of the 3D Architectures for Semiconductor Integration and Packaging Conference.","author":"RTI.","year":"2004","unstructured":"RTI. 2004 --2007 . Proceedings of the 3D Architectures for Semiconductor Integration and Packaging Conference. RTI. 2004--2007. Proceedings of the 3D Architectures for Semiconductor Integration and Packaging Conference."},{"key":"e_1_2_1_8_1","volume-title":"Proceedings of Advanced Metallization Conference, MINI-Workshop.","author":"Schaper L.","year":"2004","unstructured":"Schaper , L. 2004 . Copper electroplated through silicon vias for 3-DIC interconnection . In Proceedings of Advanced Metallization Conference, MINI-Workshop. Schaper, L. 2004. Copper electroplated through silicon vias for 3-DIC interconnection. In Proceedings of Advanced Metallization Conference, MINI-Workshop."},{"key":"e_1_2_1_9_1","volume-title":"Proceedings of the 3D Technology, Modeling, and Process Symposium.","author":"SEMANTIC.","year":"2004","unstructured":"SEMANTIC. 2004 . Proceedings of the 3D Technology, Modeling, and Process Symposium. SEMANTIC. 2004. Proceedings of the 3D Technology, Modeling, and Process Symposium."},{"volume-title":"IEEE International Electronic Devices Meeting Conference Digest Technology Papers, 363--366","author":"Topol A. W.","key":"e_1_2_1_10_1","unstructured":"Topol , A. W. , La Tulipe , D. C. , Shi , L. , Alam , S. M. , Frank , D. J. , Steen , S. E. , Vichiconti , J. , Posillico , D. , Cobb , M. , Medd , S. , Patel , J. , Goma , S. , DiMilia , D. , Robson , M. T. , Duch , E. , Farinelli , M , Wang , C. , Conti , R. A. , Canaperi , L. , Deligianni , A. , Kummar , A. , Kwietniak , K. T. , D'emic , C. , Ott , J. , Young , A. M. , Guarini , K. W. , and Leong , M . 2005. Enabling SOI-based assembly technology for three-dimensional (3D) integrated circuits (ICs) . In IEEE International Electronic Devices Meeting Conference Digest Technology Papers, 363--366 . Topol, A. W., La Tulipe, D. C., Shi, L., Alam, S. M., Frank, D. J., Steen, S. E., Vichiconti, J., Posillico, D., Cobb, M., Medd, S., Patel, J., Goma, S., DiMilia, D., Robson, M. T., Duch, E., Farinelli, M, Wang, C., Conti, R. A., Canaperi, L., Deligianni, A., Kummar, A., Kwietniak, K. T., D'emic, C., Ott, J., Young, A. M., Guarini, K. W., and Leong, M. 2005. Enabling SOI-based assembly technology for three-dimensional (3D) integrated circuits (ICs). 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