{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:34:53Z","timestamp":1750307693298,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":14,"publisher":"ACM","license":[{"start":{"date-parts":[[2008,10,19]],"date-time":"2008-10-19T00:00:00Z","timestamp":1224374400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2008,10,19]]},"DOI":"10.1145\/1450135.1450153","type":"proceedings-article","created":{"date-parts":[[2008,10,22]],"date-time":"2008-10-22T12:25:44Z","timestamp":1224678344000},"page":"73-78","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["Distributed and low-power synchronization architecture for embedded multiprocessors"],"prefix":"10.1145","author":[{"given":"Chenjie","family":"Yu","sequence":"first","affiliation":[{"name":"University of Maryland, College Park, MD, USA"}]},{"given":"Peter","family":"Petrov","sequence":"additional","affiliation":[{"name":"University of Maryland, College Park, MD, USA"}]}],"member":"320","published-online":{"date-parts":[[2008,10,19]]},"reference":[{"doi-asserted-by":"publisher","key":"e_1_3_2_1_1_1","DOI":"10.5555\/789083.1022890"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_2_1","DOI":"10.1109\/TVLSI.2006.884147"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_3_1","DOI":"10.1145\/1289881.1289908"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_4_1","DOI":"10.1145\/502217.502242"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_5_1","DOI":"10.1145\/1289881.1289909"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_6_1","DOI":"10.1109\/HPCA.2004.10018"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_7_1","DOI":"10.1145\/1228784.1228900"},{"key":"e_1_3_2_1_8_1","first-page":"633","volume-title":"Automation and Test in Europe (DATE)","author":"Saglam B.","year":"2001","unstructured":"B. Saglam and V. Mooney , \" System-on-a-chip processor synchronization support in hardware\", in Design , Automation and Test in Europe (DATE) , pp. 633 -- 641 , 2001 . B. Saglam and V. Mooney, \"System-on-a-chip processor synchronization support in hardware\", in Design, Automation and Test in Europe (DATE), pp. 633--641, 2001."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_9_1","DOI":"10.1145\/130823.130824"},{"key":"e_1_3_2_1_10_1","first-page":"34","volume-title":"International Symposium on Workload Characterization","author":"Li M-L.","year":"2005","unstructured":"M-L. Li , R. Sasanka , S. Adve , Y-K. Chen and E. Debes , \" The ALPBench benchmark suite for complex multimedia applications \", in International Symposium on Workload Characterization , pp. 34 -- 45 , October 2005 . M-L. Li, R. Sasanka, S. Adve, Y-K. Chen and E. Debes, \"The ALPBench benchmark suite for complex multimedia applications\", in International Symposium on Workload Characterization, pp. 34--45, October 2005."},{"key":"e_1_3_2_1_11_1","first-page":"330","volume-title":"30th MICRO","author":"Lee C.","year":"1997","unstructured":"C. Lee , M. Potkonjak and W. H. Mangione-Smith , \" MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems \", in 30th MICRO , pp. 330 -- 335 , December 1997 . C. Lee, M. Potkonjak and W. H. Mangione-Smith, \"MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems\", in 30th MICRO, pp. 330--335, December 1997."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_12_1","DOI":"10.5555\/1128020.1128563"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_13_1","DOI":"10.1109\/MM.2006.82"},{"key":"e_1_3_2_1_14_1","volume-title":"HP Laboratories Palo Alto","author":"Tarjan D.","year":"2006","unstructured":"D. Tarjan , S. Thoziyoor and N. Jouppi , \" CACTI 4.0: An Integrated Cache Timing, Power and Area Model\", Technical report , HP Laboratories Palo Alto , June 2006 . D. Tarjan, S. Thoziyoor and N. Jouppi, \"CACTI 4.0: An Integrated Cache Timing, Power and Area Model\", Technical report, HP Laboratories Palo Alto, June 2006."}],"event":{"sponsor":["ACM Association for Computing Machinery","SIGBED ACM Special Interest Group on Embedded Systems","SIGDA ACM Special Interest Group on Design Automation","SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"],"acronym":"ESWEEK 08","name":"ESWEEK 08: Fourth Embedded Systems Week","location":"Atlanta GA USA"},"container-title":["Proceedings of the 6th IEEE\/ACM\/IFIP international conference on Hardware\/Software codesign and system synthesis"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1450135.1450153","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1450135.1450153","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:29:55Z","timestamp":1750253395000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1450135.1450153"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,10,19]]},"references-count":14,"alternative-id":["10.1145\/1450135.1450153","10.1145\/1450135"],"URL":"https:\/\/doi.org\/10.1145\/1450135.1450153","relation":{},"subject":[],"published":{"date-parts":[[2008,10,19]]},"assertion":[{"value":"2008-10-19","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}