{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,27]],"date-time":"2025-08-27T15:50:09Z","timestamp":1756309809554,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":25,"publisher":"ACM","license":[{"start":{"date-parts":[[2008,10,25]],"date-time":"2008-10-25T00:00:00Z","timestamp":1224892800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2008,10,25]]},"DOI":"10.1145\/1454115.1454124","type":"proceedings-article","created":{"date-parts":[[2008,10,28]],"date-time":"2008-10-28T12:18:35Z","timestamp":1225196315000},"page":"43-51","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":63,"title":["Core cannibalization architecture"],"prefix":"10.1145","author":[{"given":"Bogdan F.","family":"Romanescu","sequence":"first","affiliation":[{"name":"Duke University, Durham, NC, USA"}]},{"given":"Daniel J.","family":"Sorin","sequence":"additional","affiliation":[{"name":"Duke University, Durham, NC, USA"}]}],"member":"320","published-online":{"date-parts":[[2008,10,25]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250720"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.37"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2005.8"},{"key":"e_1_3_2_1_4_1","volume-title":"Proceedings of the SIAM Conference on Parallel Processing","author":"Carter L.","year":"1999","unstructured":"L. Carter , J. Feo , and A. Snavely . Performance and Programming Experience on the Tera MTA . In Proceedings of the SIAM Conference on Parallel Processing , Mar. 1999 . L. Carter, J. Feo, and A. Snavely. Performance and Programming Experience on the Tera MTA. In Proceedings of the SIAM Conference on Parallel Processing, Mar. 1999."},{"key":"e_1_3_2_1_5_1","unstructured":"Cisco Systems. Cisco Carrier Router System. http:\/\/www.cisco.com\/application\/pdf\/en\/us\/guest\/products\/ps5763\/c1031\/cdcco% nt_0900aecd800f8118.pdf Oct. 2006.  Cisco Systems. Cisco Carrier Router System. http:\/\/www.cisco.com\/application\/pdf\/en\/us\/guest\/products\/ps5763\/c1031\/cdcco% nt_0900aecd800f8118.pdf Oct. 2006."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1450095.1450099"},{"key":"e_1_3_2_1_7_1","volume-title":"Computer Architecture: A Quantitative Approach. Morgan Kaufmann","author":"Hennessy J. L.","year":"2003","unstructured":"J. L. Hennessy and D. A. Patterson . Computer Architecture: A Quantitative Approach. Morgan Kaufmann , third edition, 2003 . J. L. Hennessy and D. A. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann, third edition, 2003."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.920580"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250686"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/774572.774629"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.35"},{"key":"e_1_3_2_1_12_1","unstructured":"D. Lampret. OpenRISC 1200 IP Core Specification Rev. 0.7. http:\/\/www.opencores.org Sept. 2001.  D. Lampret. OpenRISC 1200 IP Core Specification Rev. 0.7. http:\/\/www.opencores.org Sept. 2001."},{"key":"e_1_3_2_1_13_1","first-page":"330","volume-title":"Proceedings of the 30th Annual IEEE\/ACM International Symposium on Microarchitecture","author":"Lee C.","year":"1997","unstructured":"C. Lee , M. Potkonjak , and W. H. Mangione-Smith . MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems . In Proceedings of the 30th Annual IEEE\/ACM International Symposium on Microarchitecture , pages 330 -- 335 , Dec. 1997 . C. Lee, M. Potkonjak, and W. H. Mangione-Smith. MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems. In Proceedings of the 30th Annual IEEE\/ACM International Symposium on Microarchitecture, pages 330--335, Dec. 1997."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373464"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.44"},{"key":"e_1_3_2_1_16_1","first-page":"22","volume-title":"SPARC SOC. In Proceedings of the IEEE Asian Solid-State Circuits Conference","author":"Shah M.","year":"2007","unstructured":"M. Shah PARC T2 : A Highly-Threaded, Power-Efficient , SPARC SOC. In Proceedings of the IEEE Asian Solid-State Circuits Conference , pages 22 -- 25 , Nov. 2007 . M. Shah et al. UltraSPARC T2: A Highly-Threaded, Power-Efficient, SPARC SOC. In Proceedings of the IEEE Asian Solid-State Circuits Conference, pages 22--25, Nov. 2007."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.5555\/946246.946573"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168868"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.435.0863"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.5555\/998680.1006725"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.5555\/1009382.1009733"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.28"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1093\/ietele\/e89-c.6.844"},{"key":"e_1_3_2_1_24_1","volume-title":"Principles of CMOS VLSI Design: A Systems Perspective","author":"Weste N.","year":"1982","unstructured":"N. Weste and K. Eshragian . Principles of CMOS VLSI Design: A Systems Perspective . Addison-Wesley Publishing Co. , 1982 . N. Weste and K. Eshragian. Principles of CMOS VLSI Design: A Systems Perspective. Addison-Wesley Publishing Co., 1982."},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346182"}],"event":{"name":"PACT '08: International Conference on Parallel Architectures and Compilation Techniques","sponsor":["ACM Association for Computing Machinery","SIGARCH ACM Special Interest Group on Computer Architecture"],"location":"Toronto Ontario Canada","acronym":"PACT '08"},"container-title":["Proceedings of the 17th international conference on Parallel architectures and compilation techniques"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1454115.1454124","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1454115.1454124","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:29:39Z","timestamp":1750253379000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1454115.1454124"}},"subtitle":["improving lifetime chip performance for multicore processors in the presence of hard faults"],"short-title":[],"issued":{"date-parts":[[2008,10,25]]},"references-count":25,"alternative-id":["10.1145\/1454115.1454124","10.1145\/1454115"],"URL":"https:\/\/doi.org\/10.1145\/1454115.1454124","relation":{},"subject":[],"published":{"date-parts":[[2008,10,25]]},"assertion":[{"value":"2008-10-25","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}