{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:34:33Z","timestamp":1750307673356,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":41,"publisher":"ACM","license":[{"start":{"date-parts":[[2008,10,25]],"date-time":"2008-10-25T00:00:00Z","timestamp":1224892800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2008,10,25]]},"DOI":"10.1145\/1454115.1454137","type":"proceedings-article","created":{"date-parts":[[2008,10,28]],"date-time":"2008-10-28T12:18:35Z","timestamp":1225196315000},"page":"144-154","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":30,"title":["Scalable and reliable communication for hardware transactional memory"],"prefix":"10.1145","author":[{"given":"Seth H.","family":"Pugsley","sequence":"first","affiliation":[{"name":"University of Utah, Salt Lake City, UT, USA"}]},{"given":"Manu","family":"Awasthi","sequence":"additional","affiliation":[{"name":"University of Utah, Salt Lake City, UT, USA"}]},{"given":"Niti","family":"Madan","sequence":"additional","affiliation":[{"name":"University of Utah, Salt Lake City, UT, USA"}]},{"given":"Naveen","family":"Muralimanohar","sequence":"additional","affiliation":[{"name":"University of Utah, Salt Lake City, UT, USA"}]},{"given":"Rajeev","family":"Balasubramonian","sequence":"additional","affiliation":[{"name":"University of Utah, Salt Lake City, UT, USA"}]}],"member":"320","published-online":{"date-parts":[[2008,10,25]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.855961"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.41"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250674"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1248377.1248398"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-30579-8_9"},{"key":"e_1_3_2_1_6_1","volume-title":"Proceedings of WMPI","author":"Cantin J.","year":"2001","unstructured":"J. Cantin , M. Lipasti , and J. Smith . Dynamic Verification of Cache Coherence Protocols . In Proceedings of WMPI , June 2001 . J. Cantin, M. Lipasti, and J. Smith. Dynamic Verification of Cache Coherence Protocols. In Proceedings of WMPI, June 2001."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.13"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250697"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346189"},{"key":"e_1_3_2_1_10_1","author":"Chung J.","year":"2006","unstructured":"J. Chung , H. Chafi , A. McDonald , C. Minh , B. Carlstrom , C. Kozyrakis , and K. Olukotun . The Common Case Transactional Behavior of Multithreaded Programs. In Proceedings of HPCA-12 , February 2006 . J. Chung, H. Chafi, A. McDonald, C. Minh, B. Carlstrom, C. Kozyrakis, and K. Olukotun. The Common Case Transactional Behavior of Multithreaded Programs. In Proceedings of HPCA-12, February 2006.","journal-title":"The Common Case Transactional Behavior of Multithreaded Programs. In Proceedings of HPCA-12"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.363382"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/PDP.2007.22"},{"volume-title":"Workshop on On- and Off-Chip Interconnection Networks for Multicore Systems (OCIN), 2006. Workshop program and report at http:\/\/www.ece.ucdavis.edu\/~ocin06\/.","author":"Dally W.","key":"e_1_3_2_1_13_1","unstructured":"W. Dally . Workshop on On- and Off-Chip Interconnection Networks for Multicore Systems (OCIN), 2006. Workshop program and report at http:\/\/www.ece.ucdavis.edu\/~ocin06\/. W. Dally. Workshop on On- and Off-Chip Interconnection Networks for Multicore Systems (OCIN), 2006. Workshop program and report at http:\/\/www.ece.ucdavis.edu\/~ocin06\/."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/EPEP.1997.634037"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1119772.1119817"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346194"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-1685-9"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1095890.1095915"},{"key":"e_1_3_2_1_20_1","volume-title":"On-Die Interconnects for Next Generation CMPs. In Workshop on On- and Off-Chip Interconnection Networks for Multicore Systems (OCIN)","author":"Kundu P.","year":"2006","unstructured":"P. Kundu . On-Die Interconnects for Next Generation CMPs. In Workshop on On- and Off-Chip Interconnection Networks for Multicore Systems (OCIN) , December 2006 . P. Kundu. On-Die Interconnects for Next Generation CMPs. In Workshop on On- and Off-Chip Interconnection Networks for Multicore Systems (OCIN), December 2006."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/319566.319567"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/359545.359563"},{"key":"e_1_3_2_1_23_1","volume-title":"Transactional Memory. Morgan &amp","author":"Larus J. R.","year":"2006","unstructured":"J. R. Larus and R. Rajwar . Transactional Memory. Morgan &amp ; Claypool , 2006 . J. R. Larus and R. Rajwar. Transactional Memory. Morgan &amp; Claypool, 2006."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859640"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.17"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.14"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346193"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250673"},{"key":"e_1_3_2_1_29_1","author":"Moore K.","year":"2006","unstructured":"K. Moore , J. Bobba , M. Moravan , M. Hill , and D. Wood . LogTM: Log-Based Transactional Memory. In Proceedings of HPCA-12 , February 2006 . K. Moore, J. Bobba, M. Moravan, M. Hill, and D. Wood. LogTM: Log-Based Transactional Memory. In Proceedings of HPCA-12, February 2006.","journal-title":"LogTM: Log-Based Transactional Memory. In Proceedings of HPCA-12"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.37"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.30"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2006.35"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379264"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605399"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.54"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/1088149.1088178"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/1073814.1073861"},{"key":"e_1_3_2_1_38_1","volume-title":"International Technology Roadmap for Semiconductors","author":"Semiconductor Industry Association","year":"2005","unstructured":"Semiconductor Industry Association . International Technology Roadmap for Semiconductors 2005 . Semiconductor Industry Association. International Technology Roadmap for Semiconductors 2005."},{"key":"e_1_3_2_1_39_1","volume-title":"Proceedings of DSN","author":"Shivakumar P.","year":"2002","unstructured":"P. Shivakumar , M. Kistler , S. Keckler , D. Burger , and L. Alvisi . Modeling the Effect of Technology Trends on the Soft Error Rate of Combinatorial Logic . In Proceedings of DSN , June 2002 . P. Shivakumar, M. Kistler, S. Keckler, D. Burger, and L. Alvisi. Modeling the Effect of Technology Trends on the Soft Error Rate of Combinatorial Logic. In Proceedings of DSN, June 2002."},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2003.1209938"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339650"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/513918.514085"}],"event":{"name":"PACT '08: International Conference on Parallel Architectures and Compilation Techniques","sponsor":["ACM Association for Computing Machinery","SIGARCH ACM Special Interest Group on Computer Architecture"],"location":"Toronto Ontario Canada","acronym":"PACT '08"},"container-title":["Proceedings of the 17th international conference on Parallel architectures and compilation techniques"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1454115.1454137","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1454115.1454137","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:29:39Z","timestamp":1750253379000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1454115.1454137"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,10,25]]},"references-count":41,"alternative-id":["10.1145\/1454115.1454137","10.1145\/1454115"],"URL":"https:\/\/doi.org\/10.1145\/1454115.1454137","relation":{},"subject":[],"published":{"date-parts":[[2008,10,25]]},"assertion":[{"value":"2008-10-25","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}