{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:34:34Z","timestamp":1750307674300,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":36,"publisher":"ACM","license":[{"start":{"date-parts":[[2008,10,25]],"date-time":"2008-10-25T00:00:00Z","timestamp":1224892800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2008,10,25]]},"DOI":"10.1145\/1454115.1454138","type":"proceedings-article","created":{"date-parts":[[2008,10,28]],"date-time":"2008-10-28T12:18:35Z","timestamp":1225196315000},"page":"155-165","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":17,"title":["Improving support for locality and fine-grain sharing in chip multiprocessors"],"prefix":"10.1145","author":[{"given":"Hemayet","family":"Hossain","sequence":"first","affiliation":[{"name":"University of Rochester, Rochester, NY, USA"}]},{"given":"Sandhya","family":"Dwarkadas","sequence":"additional","affiliation":[{"name":"University of Rochester, Rochester, NY, USA"}]},{"given":"Michael C.","family":"Huang","sequence":"additional","affiliation":[{"name":"University of Rochester, Rochester, NY, USA"}]}],"member":"320","published-online":{"date-parts":[[2008,10,25]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2003.1178046"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/225535.225537"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/277851.277897"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.10"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICDM.2006.15"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.17"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346210"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.39"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.5555\/956417.956577"},{"key":"e_1_3_2_1_10_1","unstructured":"Intel Corporation. Introducing the 45nm Next-Generation Intel Core Microarchitecture. http:\/\/www.intel.com\/technology\/architecture-silicon\/intel64\/45nmcore2_whitepaper.pdf.  Intel Corporation. Introducing the 45nm Next-Generation Intel Core Microarchitecture. http:\/\/www.intel.com\/technology\/architecture-silicon\/intel64\/45nmcore2_whitepaper.pdf."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"crossref","unstructured":"Intel Corporation. Power delivery for high-performance microprocessors. http:\/\/www.intel.com\/technology\/itj\/2005\/volume09issue04\/art02_powerdelivery\/p03_powerdelivery.htm 2005.  Intel Corporation. Power delivery for high-performance microprocessors. http:\/\/www.intel.com\/technology\/itj\/2005\/volume09issue04\/art02_powerdelivery\/p03_powerdelivery.htm 2005.","DOI":"10.1535\/itj.0904.02"},{"key":"e_1_3_2_1_12_1","unstructured":"Standard Performance Evaluation Corporation. Specjbb2005. http:\/\/www.spec.org\/jbb2005\/ 2005.  Standard Performance Evaluation Corporation. Specjbb2005. http:\/\/www.spec.org\/jbb2005\/ 2005."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/165123.165146"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.27"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/224056.224072"},{"key":"e_1_3_2_1_16_1","unstructured":"The Apache Software Foundation. Apache. http:\/\/www.apache.org\/ 2008.  The Apache Software Foundation. Apache. http:\/\/www.apache.org\/ 2008."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.5555\/520549.822758"},{"key":"e_1_3_2_1_19_1","first-page":"156","volume-title":"Proceedings of the 6th International Symposium on High Performance Computer Architecture","author":"Kaxiras S.","year":"2000"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605420"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.35"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/300979.300994"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.982916"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859642"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/1105734.1105747"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.34"},{"volume-title":"EE Times","year":"2003","author":"Merritt R.","key":"e_1_3_2_1_27_1"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2007.70756"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/279358.279386"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.30"},{"key":"e_1_3_2_1_31_1","unstructured":"Intel News Release. Intel research advances \"era of tera\". http:\/\/www.intel.com\/pressroom\/archive\/releases\/20070204comp.htm Feb. 2007.  Intel News Release. Intel research advances \"era of tera\". http:\/\/www.intel.com\/pressroom\/archive\/releases\/20070204comp.htm Feb. 2007."},{"key":"e_1_3_2_1_32_1","unstructured":"Sun News Release. Sun expands solaris\/sparc cmt innovation leadership. http:\/\/www.sun.com\/aboutsun\/pr\/2007-01\/sunflash.20070118.3.xml Jan. 2007.  Sun News Release. Sun expands solaris\/sparc cmt innovation leadership. http:\/\/www.sun.com\/aboutsun\/pr\/2007-01\/sunflash.20070118.3.xml Jan. 2007."},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/165123.165147"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/319151.319153"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/319151.319153"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.491460"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.53"}],"event":{"name":"PACT '08: International Conference on Parallel Architectures and Compilation Techniques","sponsor":["ACM Association for Computing Machinery","SIGARCH ACM Special Interest Group on Computer Architecture"],"location":"Toronto Ontario Canada","acronym":"PACT '08"},"container-title":["Proceedings of the 17th international conference on Parallel architectures and compilation techniques"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1454115.1454138","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1454115.1454138","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:29:39Z","timestamp":1750253379000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1454115.1454138"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,10,25]]},"references-count":36,"alternative-id":["10.1145\/1454115.1454138","10.1145\/1454115"],"URL":"https:\/\/doi.org\/10.1145\/1454115.1454138","relation":{},"subject":[],"published":{"date-parts":[[2008,10,25]]},"assertion":[{"value":"2008-10-25","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}