{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T16:47:03Z","timestamp":1773247623192,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":22,"publisher":"ACM","license":[{"start":{"date-parts":[[2008,10,25]],"date-time":"2008-10-25T00:00:00Z","timestamp":1224892800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2008,10,25]]},"DOI":"10.1145\/1454115.1454140","type":"proceedings-article","created":{"date-parts":[[2008,10,28]],"date-time":"2008-10-28T12:18:35Z","timestamp":1225196315000},"page":"166-176","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":161,"title":["Edge-centric modulo scheduling for coarse-grained reconfigurable architectures"],"prefix":"10.1145","author":[{"given":"Hyunchul","family":"Park","sequence":"first","affiliation":[{"name":"University of Michigan, Ann Arbor, MI, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kevin","family":"Fan","sequence":"additional","affiliation":[{"name":"University of Michigan, Ann Arbor, MI, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Scott A.","family":"Mahlke","sequence":"additional","affiliation":[{"name":"University of Michigan, Ann Arbor, MI, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Taewook","family":"Oh","sequence":"additional","affiliation":[{"name":"Samsung Advanced Institute of Technology, Kiheung, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Heeseok","family":"Kim","sequence":"additional","affiliation":[{"name":"Samsung Advanced Institute of Technology, Kiheung, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hong-seok","family":"Kim","sequence":"additional","affiliation":[{"name":"Samsung Advanced Institute of Technology, Kiheung, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2008,10,25]]},"reference":[{"key":"e_1_3_2_1_1_1","first-page":"363","volume-title":"Proc. of the 2006 Design, Automation and Test in Europe","author":"Ahn M.","year":"2006","unstructured":"M. Ahn , J. W. Yoon , Y. Paek , Y. Kim , M. Kiemb , and K. Choi . A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures . In Proc. of the 2006 Design, Automation and Test in Europe , pages 363 -- 368 , Mar. 2006 . M. Ahn, J. W. Yoon, Y. Paek, Y. Kim, M. Kiemb, and K. Choi. A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures. In Proc. of the 2006 Design, Automation and Test in Europe, pages 363--368, Mar. 2006."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168875"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.5555\/549928.795752"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.5555\/225160.225210"},{"key":"e_1_3_2_1_5_1","unstructured":"ElementCXI. http:\/\/www.elementcxi.org.  ElementCXI. http:\/\/www.elementcxi.org."},{"key":"e_1_3_2_1_6_1","volume-title":"Bulldog: A Compiler for VLIW Architectures","author":"Ellis J.","year":"1985","unstructured":"J. Ellis . Bulldog: A Compiler for VLIW Architectures . MIT Press , Cambridge, MA , 1985 . J. Ellis. Bulldog: A Compiler for VLIW Architectures. MIT Press, Cambridge, MA, 1985."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/300979.300982"},{"key":"e_1_3_2_1_8_1","first-page":"32","volume-title":"IEEE 18th Hot Chips Symposium","author":"Jones A. M.","year":"2006","unstructured":"A. M. Jones and M. Butts . Teroops hardware: A new massively-parallel mimd computing fabric ic . In IEEE 18th Hot Chips Symposium , pages 32 -- 41 , Aug. 2006 . A. M. Jones and M. Butts. Teroops hardware: A new massively-parallel mimd computing fabric ic. In IEEE 18th Hot Chips Symposium, pages 32--41, Aug. 2006."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/514191.514209"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2003.1173050"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/291069.291018"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.5555\/774861.774874"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.5555\/646664.700601"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.5555\/789083.1022741"},{"key":"e_1_3_2_1_15_1","first-page":"622","volume-title":"Proc. of the 2005 International Conference on Field Programmable Logic and Applications","author":"Mei B.","year":"2005","unstructured":"B. Mei , F. Veredas , and B. Masschelein . Mapping an H.264\/AVC decoder onto the ADRES reconfigurable architecture . In Proc. of the 2005 International Conference on Field Programmable Logic and Applications , pages 622 -- 625 , Aug. 2005 . B. Mei, F. Veredas, and B. Masschelein. Mapping an H.264\/AVC decoder onto the ADRES reconfigurable architecture. In Proc. of the 2005 International Conference on Field Programmable Logic and Applications, pages 622--625, Aug. 2005."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168876"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.5555\/290940.290966"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1176760.1176778"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.5555\/968880.969243"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/192724.192731"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/360128.360142"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.997877"}],"event":{"name":"PACT '08: International Conference on Parallel Architectures and Compilation Techniques","location":"Toronto Ontario Canada","acronym":"PACT '08","sponsor":["ACM Association for Computing Machinery","SIGARCH ACM Special Interest Group on Computer Architecture"]},"container-title":["Proceedings of the 17th international conference on Parallel architectures and compilation techniques"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1454115.1454140","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1454115.1454140","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:29:39Z","timestamp":1750253379000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1454115.1454140"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,10,25]]},"references-count":22,"alternative-id":["10.1145\/1454115.1454140","10.1145\/1454115"],"URL":"https:\/\/doi.org\/10.1145\/1454115.1454140","relation":{},"subject":[],"published":{"date-parts":[[2008,10,25]]},"assertion":[{"value":"2008-10-25","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}