{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T12:11:17Z","timestamp":1763467877906,"version":"3.41.0"},"reference-count":56,"publisher":"Association for Computing Machinery (ACM)","issue":"5","license":[{"start":{"date-parts":[[2008,9,1]],"date-time":"2008-09-01T00:00:00Z","timestamp":1220227200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["Queue"],"published-print":{"date-parts":[[2008,9]]},"abstract":"<jats:p>TM (transactional memory) is a concurrency control paradigm that provides atomic and isolated execution for regions of code. TM is considered by many researchers to be one of the most promising solutions to address the problem of programming multicore processors. Its most appealing feature is that most programmers only need to reason locally about shared data accesses, mark the code region to be executed transactionally, and let the underlying system ensure the correct concurrent execution. This model promises to provide the scalability of fine-grain locking, while avoiding common pitfalls of lock composition such as deadlock. In this article we explore the performance of a highly optimized STM and observe that the overall performance of TM is significantly worse at low levels of parallelism, which is likely to limit the adoption of this programming paradigm.<\/jats:p>","DOI":"10.1145\/1454456.1454466","type":"journal-article","created":{"date-parts":[[2008,10,28]],"date-time":"2008-10-28T12:18:30Z","timestamp":1225196310000},"page":"46-58","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":110,"title":["Software Transactional Memory: Why Is It Only a Research Toy?"],"prefix":"10.1145","volume":"6","author":[{"given":"Calin","family":"Cascaval","sequence":"first","affiliation":[]},{"given":"Colin","family":"Blundell","sequence":"additional","affiliation":[]},{"given":"Maged","family":"Michael","sequence":"additional","affiliation":[]},{"given":"Harold W.","family":"Cain","sequence":"additional","affiliation":[]},{"given":"Peng","family":"Wu","sequence":"additional","affiliation":[]},{"given":"Stefanie","family":"Chiras","sequence":"additional","affiliation":[]},{"given":"Siddhartha","family":"Chatterjee","sequence":"additional","affiliation":[{"name":"STEC"}]}],"member":"320","published-online":{"date-parts":[[2008,9]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/165123.165164"},{"key":"e_1_2_1_2_1","doi-asserted-by":"crossref","unstructured":"Larus J.R. Rajwar R. 2006. Transactional Memory. Morgan Claypool.","DOI":"10.1007\/978-3-031-01719-3"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1007\/11864219_14"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/949305.949340"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/872035.872048"},{"key":"e_1_2_1_6_1","volume-title":"prototype edition 2.0","author":"Intel","year":"2008","unstructured":"Intel C++ STM compiler, prototype edition 2.0.; http:\/\/softwarecommunity.intel.com\/articles\/eng\/1460.htm\/ (2008)."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1122971.1123001"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/224964.224987"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250667"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.24"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.5555\/998680.1006711"},{"key":"e_1_2_1_13_1","unstructured":"See reference 1."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250673"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2006.1598134"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346204"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.13"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2008.4523067"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.34"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168900"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.9"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250676"},{"key":"e_1_2_1_23_1","unstructured":"STAMP benchmark suite. 2007. http:\/\/stamp.stanford.edu\/."},{"key":"e_1_2_1_24_1","unstructured":"The Lonestar benchmark suite. 2008. http:\/\/iss.ices.utexas.edu\/lonestar\/."},{"key":"e_1_2_1_25_1","unstructured":"(IBM) XL C\/C++ for Transactional Memory for AIX. 2008. www.alphaworks.ibm.com\/tech\/xlcstm\/."},{"key":"e_1_2_1_26_1","unstructured":"See reference 6."},{"key":"e_1_2_1_27_1","unstructured":"See reference 3."},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2006.18"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250734.1250759"},{"key":"e_1_2_1_30_1","unstructured":"See reference 14."},{"key":"e_1_2_1_31_1","unstructured":"See reference 23."},{"key":"e_1_2_1_32_1","unstructured":"See reference 25."},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","unstructured":"Wu P. Michael M.M. von Praun C. Nakaike T. Bordawekar R. Cain H.W. Cascaval C. Chatterjee S. Chiras S. Hou R. Mergen M. Shen X. Spear M.F. Wang H.Y. Wang K. 2008. Compiler and runtime techniques for software transactional memory optimization. To appear in Concurrency and Computation: Practice and Experience. 10.1002\/cpe.v21:1","DOI":"10.1002\/cpe.v21:1"},{"key":"e_1_2_1_34_1","unstructured":"See reference 6."},{"key":"e_1_2_1_35_1","unstructured":"See reference 3."},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/1378533.1378582"},{"key":"e_1_2_1_37_1","unstructured":"See reference 36."},{"key":"e_1_2_1_38_1","unstructured":"See reference 25."},{"key":"e_1_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250734.1250744"},{"key":"e_1_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/1133981.1133984"},{"key":"e_1_2_1_41_1","unstructured":"See reference 39."},{"key":"e_1_2_1_42_1","unstructured":"See reference 40."},{"key":"e_1_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1145\/1378533.1378589"},{"key":"e_1_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1145\/224964.224987"},{"key":"e_1_2_1_45_1","unstructured":"See reference 3."},{"key":"e_1_2_1_46_1","unstructured":"See reference 5."},{"key":"e_1_2_1_47_1","unstructured":"See reference 4."},{"key":"e_1_2_1_48_1","unstructured":"See reference 7."},{"key":"e_1_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1145\/1248377.1248415"},{"key":"e_1_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.5555\/1299042.1299063"},{"key":"e_1_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.1145\/1378533.1378583"},{"key":"e_1_2_1_52_1","volume-title":"Proceedings of the ACM SIGPLAN Workshop on Transactional Computing (August).","author":"Felber P.","year":"2007","unstructured":"Felber, P., Fetzer, C., Mueller, U., Riegel, T., Suesskraut, M., Sturzrehm, H. 2007. Transactifying applications using an open compiler framework. In Proceedings of the ACM SIGPLAN Workshop on Transactional Computing (August)."},{"key":"e_1_2_1_53_1","unstructured":"See reference 50."},{"key":"e_1_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2007.4"},{"key":"e_1_2_1_55_1","unstructured":"See reference 36."},{"key":"e_1_2_1_56_1","unstructured":"See reference 6."},{"key":"e_1_2_1_57_1","unstructured":"See reference 8."}],"container-title":["Queue"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1454456.1454466","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1454456.1454466","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T12:45:56Z","timestamp":1750250756000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1454456.1454466"}},"subtitle":["The promise of STM may likely be undermined by its overheads and workload applicabilities."],"short-title":[],"issued":{"date-parts":[[2008,9]]},"references-count":56,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2008,9]]}},"alternative-id":["10.1145\/1454456.1454466"],"URL":"https:\/\/doi.org\/10.1145\/1454456.1454466","relation":{},"ISSN":["1542-7730","1542-7749"],"issn-type":[{"type":"print","value":"1542-7730"},{"type":"electronic","value":"1542-7749"}],"subject":[],"published":{"date-parts":[[2008,9]]},"assertion":[{"value":"2008-09-01","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}