{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:34:59Z","timestamp":1750307699172,"version":"3.41.0"},"reference-count":33,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2009,1,1]],"date-time":"2009-01-01T00:00:00Z","timestamp":1230768000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2009,1]]},"abstract":"<jats:p>\n            Process variations due to lens aberrations are to a large extent systematic, and can be modeled for purposes of analyses and optimizations in the design phase. Traditionally, variations induced by lens aberrations have been considered random due to their small extent. However, as process margins reduce, and as improvements in reticle enhancement techniques control variations due to other sources with increased efficacy, lens aberration-induced variations gain importance. For example, our experiments indicate that delays of most cells in the Artisan TSMC 90nm library are affected by 2--8% due to lens aberration. Aberration-induced variations are systematic and depend on the location in the lens field. In this article, we first propose an aberration-aware timing analysis flow that accounts for aberration-induced cell delay variations. We then propose an aberration-aware timing-driven analytical placement approach that utilizes the predictable slow and fast regions created on the chip due to aberration to improve cycle time. We study the dependence of our improvement on chip size, as well as use of the technique along with field blading which allows partial reticle exposure. We evaluate our technique on two testcases,\n            <jats:italic>AES<\/jats:italic>\n            and\n            <jats:italic>JPEG<\/jats:italic>\n            implemented in 90\n            <jats:italic>nm<\/jats:italic>\n            technology. The proposed technique reduces cycle time by 4.322% (80ps) at the cost of 1.587% increase in trial-routed wirelength for AES. On JPEG, we observe a cycle time reduction of 5.182% (132ps) at the cost of 1.095% increase in trial-routed wirelength.\n          <\/jats:p>","DOI":"10.1145\/1455229.1455245","type":"journal-article","created":{"date-parts":[[2009,1,29]],"date-time":"2009-01-29T13:48:36Z","timestamp":1233236916000},"page":"1-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Lens aberration aware placement for timing yield"],"prefix":"10.1145","volume":"14","author":[{"given":"Andrew B.","family":"Kahng","sequence":"first","affiliation":[{"name":"University of California at San Diego"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chul-Hong","family":"Park","sequence":"additional","affiliation":[{"name":"University of California at San Diego"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Puneet","family":"Sharma","sequence":"additional","affiliation":[{"name":"Freescale Semiconductor, Inc."}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Qinke","family":"Wang","sequence":"additional","affiliation":[{"name":"Magma Design Automation, Inc."}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2009,1,23]]},"reference":[{"doi-asserted-by":"publisher","key":"e_1_2_1_1_1","DOI":"10.1117\/12.569722"},{"doi-asserted-by":"publisher","key":"e_1_2_1_2_1","DOI":"10.1147\/rd.411.0057"},{"doi-asserted-by":"publisher","key":"e_1_2_1_3_1","DOI":"10.1145\/1065579.1065791"},{"doi-asserted-by":"publisher","key":"e_1_2_1_4_1","DOI":"10.1145\/277044.277119"},{"volume-title":"Proceedings of the IEEE International Conference on Computer-Aided Design. 20--24","author":"Etawil H.","unstructured":"Etawil , H. , Areibi , S. , and Vannelli , A . 1999. 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G. , Laan , H. , Schoot , J. , Bouchoms , I. , and Geha , B . 1999. Understanding systematic and random CD variations using predictive modelling techniques . In Proceedings of the SPIE Conference on Optical Microlithography. 162--175 . Flagello, D. G., Laan, H., Schoot, J., Bouchoms, I., and Geha, B. 1999. Understanding systematic and random CD variations using predictive modelling techniques. In Proceedings of the SPIE Conference on Optical Microlithography. 162--175.","key":"e_1_2_1_7_1"},{"volume-title":"Proceedings of the SPIE Conference on Optical Microlithography. 368--381","author":"Gortych J.","unstructured":"Gortych , J. and Williamson , D . 1991. Effects of higher-order aberrations on the process window . In Proceedings of the SPIE Conference on Optical Microlithography. 368--381 . Gortych, J. and Williamson, D. 1991. Effects of higher-order aberrations on the process window. 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High NA and low residual aberration projection lens for duv scanner . In Proceedings of the SPIE Conference on Optical Microlithography. 687--695 . Matsuyama, T., Shibazaki, Y., Ohmura, Y., and Suzuki, T. 2002. High NA and low residual aberration projection lens for duv scanner. In Proceedings of the SPIE Conference on Optical Microlithography. 687--695.","key":"e_1_2_1_22_1"},{"unstructured":"Naylor W. Donelley S. and Sha L. 2001. Non-linear optimization system and method for wire length and delay optimization for an automatic electric circuit placer. US Patent 6301693.  Naylor W. Donelley S. and Sha L. 2001. Non-linear optimization system and method for wire length and delay optimization for an automatic electric circuit placer. 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