{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,29]],"date-time":"2025-10-29T03:25:09Z","timestamp":1761708309922,"version":"3.41.0"},"reference-count":9,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2009,1,1]],"date-time":"2009-01-01T00:00:00Z","timestamp":1230768000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2009,1]]},"abstract":"<jats:p>This article proposes a low-cost, low-power multistandard video decoder for high definition (HD) video applications. The proposed design supports multiple-standard (JPEG baseline, MPEG-1\/2\/4 Simple Profile (SP), and H.264 Baseline Profile (BP)) video decoding through interactive parsing control and common parameter bus interface. In order to reduce hardware cost, the shared adder-based structure and reusable data management are proposed to achieve hardware sharing and reduce internal memory size, respectively. In addition, the proposed design is optimized through reducing memory bandwidth by increasing both data reuse amount and burst length of memory access as well as eliminating cycle overhead in data access for supporting HD video decoding with single AHB-based SDR memory. The proposed 252Kgates\/4.9kB\/71mW\/0.13\u03bcm multi-standard video decoder reduces 72% in gate count and 87% in power consumption as compared to the state-of-the-art design, when operating at 120MHz for real-time HD1080 video decoding with single AHB-based SDR memory.<\/jats:p>","DOI":"10.1145\/1455229.1455246","type":"journal-article","created":{"date-parts":[[2009,1,29]],"date-time":"2009-01-29T13:48:36Z","timestamp":1233236916000},"page":"1-17","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["A 252Kgates\/4.9Kbytes SRAM\/71mW multistandard video decoder for high definition video applications"],"prefix":"10.1145","volume":"14","author":[{"given":"Chih-Da","family":"Chien","sequence":"first","affiliation":[{"name":"National Chung Cheng University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Cheng-An","family":"Chien","sequence":"additional","affiliation":[{"name":"National Chung Cheng University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jui-Chin","family":"Chu","sequence":"additional","affiliation":[{"name":"National Chung Cheng University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jiun-In","family":"Guo","sequence":"additional","affiliation":[{"name":"National Chung Cheng University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ching-Hwa","family":"Cheng","sequence":"additional","affiliation":[{"name":"Feng-Chia University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2009,1,23]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"3","author":"Chen T. W.","unstructured":"Chen , T. W. , Huang , Y. W. , Chen , T. C. , Chen , Y. H. , Tsai , C. Y. , and Chen , L. G . 2005. Architecture design of H.264\/AVC decoder with hybrid task pipelining for high definition videos . In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) , Vol. 3 . 2931--2934. Chen, T. W., Huang, Y. W., Chen, T. C., Chen, Y. H., Tsai, C. Y., and Chen, L. G. 2005. Architecture design of H.264\/AVC decoder with hybrid task pipelining for high definition videos. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Vol. 3. 2931--2934."},{"volume-title":"Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC). 282--283","author":"Chien C. D.","key":"e_1_2_1_2_1","unstructured":"Chien , C. D. , Lin , C. C. , Shih , Y. H. , Chen , H. C. , Huang , C. J. , Yu , C. Y. , Chen , C. L. , Cheng , C. H. , and Guo , J. I . 2007. A 252K Gates\/71mW multi-standard multi-channel video decoder for high definition video applications . In Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC). 282--283 . Chien, C. D., Lin, C. C., Shih, Y. H., Chen, H. C., Huang, C. J., Yu, C. Y., Chen, C. L., Cheng, C. H., and Guo, J. I. 2007. A 252K Gates\/71mW multi-standard multi-channel video decoder for high definition video applications. In Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC). 282--283."},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2006.881873"},{"volume-title":"Proceedings of the IEEE International Conference on Multimedia &amp; Expo (ICME). 1211--1214","author":"Chien C. D.","key":"e_1_2_1_4_1","unstructured":"Chien , C. D. , Wang , C. W. , Lin , C. C. , Hsieh , T. W. , Chu , Y. H. , and Guo , J. I . 2007. A low latency memory controller for video coding systems . In Proceedings of the IEEE International Conference on Multimedia &amp; Expo (ICME). 1211--1214 . Chien, C. D., Wang, C. W., Lin, C. C., Hsieh, T. W., Chu, Y. H., and Guo, J. I. 2007. A low latency memory controller for video coding systems. In Proceedings of the IEEE International Conference on Multimedia &amp; Expo (ICME). 1211--1214."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2004.825542"},{"volume-title":"Proceedings of the IEEE International Symposium on Consumer Electronics (ISCE). 385--389","author":"Hu Y.","key":"e_1_2_1_6_1","unstructured":"Hu , Y. , Simpson , A. , McAdoo , K. , and Cush , J . 2004. A high definition H.264\/AVC hardware video decoder core for multimedia SoC's . In Proceedings of the IEEE International Symposium on Consumer Electronics (ISCE). 385--389 . Hu, Y., Simpson, A., McAdoo, K., and Cush, J. 2004. A high definition H.264\/AVC hardware video decoder core for multimedia SoC's. In Proceedings of the IEEE International Symposium on Consumer Electronics (ISCE). 385--389."},{"volume-title":"Proceedings of the IEEE Internatoinal Symposium on Circuits and Systems (ISCAS).","author":"Kang H. Y.","key":"e_1_2_1_7_1","unstructured":"Kang , H. Y. , Jeong , K. A. , Bae , J. Y. , Lee , Y. S. , and Lee , S. H . 2004. MPEG4 AVC\/H.264 decoder with scalable bus architecture and dual memory controller . In Proceedings of the IEEE Internatoinal Symposium on Circuits and Systems (ISCAS). vol. II . 145--148. Kang, H. Y., Jeong, K. A., Bae, J. Y., Lee, Y. S., and Lee, S. H. 2004. MPEG4 AVC\/H.264 decoder with scalable bus architecture and dual memory controller. In Proceedings of the IEEE Internatoinal Symposium on Circuits and Systems (ISCAS). vol. II. 145--148."},{"volume-title":"Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC). 406--407","author":"Lin C. C","key":"e_1_2_1_8_1","unstructured":"Lin , C. C , Guo , J. I. , Chang , H. C. , Yang , Y. C. , Chen , J. W. , Tsai , M. C. , and Wang , J. S . 2006. A 160kGate 4.5kB SRAM H.264 video decoder for HDTV applications . In Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC). 406--407 . Lin, C. C, Guo, J. I., Chang, H. C., Yang, Y. C., Chen, J. W., Tsai, M. C., and Wang, J. S. 2006. A 160kGate 4.5kB SRAM H.264 video decoder for HDTV applications. In Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC). 406--407."},{"volume-title":"Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC). 402--403","author":"Liu T. M.","key":"e_1_2_1_9_1","unstructured":"Liu , T. M. , Lin , T. A. , Wang , S. Z. , Lee , W. P. , Hou , K. C. , Yang , J. Y. , and Lee , C. Y . 2006. A 125&mu;W, Fully Scalable MPEG-2 and H.264\/AVC video decoder for mobile applications . In Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC). 402--403 . Liu, T. M., Lin, T. A., Wang, S. Z., Lee, W. P., Hou, K. C., Yang, J. Y., and Lee, C. Y. 2006. A 125&mu;W, Fully Scalable MPEG-2 and H.264\/AVC video decoder for mobile applications. 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