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While these designs can effectively detect and correct memory faults such as transient errors and single-bit defects, their use bears a significant cost overhead. In this article, we propose a novel partial memory protection scheme that provides high-coverage fault protection for program code and data, but with much lower cost than traditional approaches. Our approach profiles program code and data usage to assess which program elements are most critical to maintaining program correctness. Critical code and variables are then placed into a limited protected storage resources. To ensure high coverage of program elements, our placement technique considers all program components simultaneously, including code, global variables, stack frames, and heap variables. The fault coverage of our approach is gauged using Monte Carlo fault-injection experiments, which confirm that our technique provides high levels of fault protection (99% coverage) with limited memory protection resources (36% protected area).<\/jats:p>","DOI":"10.1145\/1455650.1455653","type":"journal-article","created":{"date-parts":[[2008,12,3]],"date-time":"2008-12-03T21:56:04Z","timestamp":1228341364000},"page":"1-24","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":19,"title":["Exploiting selective placement for low-cost memory protection"],"prefix":"10.1145","volume":"5","author":[{"given":"Mojtaba","family":"Mehrara","sequence":"first","affiliation":[{"name":"Advanced Computer Architecture Lab, University of Michigan, Ann Arbor, MI"}]},{"given":"Todd","family":"Austin","sequence":"additional","affiliation":[{"name":"Advanced Computer Architecture Lab, University of Michigan, Ann Arbor, MI"}]}],"member":"320","published-online":{"date-parts":[[2008,12]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.982917"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2002.1175845"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.243.0390"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/291069.291036"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2003.821938"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.282.0124"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1120725.1121000"},{"volume-title":"Proceedings of the 1st Workshop on Architectural Reliability (WAR-1).","author":"Constantinides K.","key":"e_1_2_1_8_1"},{"volume-title":"Proceedings of the International Workshop on Memory Technology, Design and Testing. 104--110","author":"Derhacobian N.","key":"e_1_2_1_9_1"},{"key":"e_1_2_1_10_1","doi-asserted-by":"crossref","unstructured":"Dupont E. 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