{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,1]],"date-time":"2025-11-01T00:26:36Z","timestamp":1761956796650,"version":"build-2065373602"},"reference-count":27,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2008,11,1]],"date-time":"2008-11-01T00:00:00Z","timestamp":1225497600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2008,11]]},"abstract":"<jats:p>Branch prediction feeds a speculative execution processor core with instructions. Branch mispredictions are inevitable and have negative effects on performance and energy consumption. With the advent of highly accurate conditional branch predictors, nonconditional branch instructions are gaining importance.<\/jats:p>\n          <jats:p>In this article, we address the prediction of procedure returns. On modern processors, procedure returns are predicted through a return address stack (RAS). The overwhelming majority of the return mispredictions are due to RAS overflows and\/or overwriting the top entries of the RAS on a mispredicted path. These sources of misprediction were addressed by previously proposed speculative return address stacks [Jourdan et al. 1996; Skadron et al. 1998]. However, the remaining misprediction rate of these RAS designs is still significant when compared to state-of-the-art conditional predictors.<\/jats:p>\n          <jats:p>We present two low-cost corruption detectors for RAS predictors. They detect RAS overflows and wrong path corruption with 100% coverage. As a consequence, when such a corruption is detected, another source can be used for predicting the return. On processors featuring a branch target buffer (BTB), this BTB can be used as a free backup predictor for predicting returns when corruption is detected.<\/jats:p>\n          <jats:p>Our experiments show that our proposal can be used to improve the behavior of all previously proposed speculative RASs. For instance, without any specific management of the speculative states on the RAS, an 8-entry BTB-backed up RAS achieves the same performance level as a state-of-the-art, but complex, 64-entry self-checkpointing RAS [Jourdan et al. 1996]. Therefore, our proposal can be used either to improve the performance of the processor or to reduce its hardware complexity.<\/jats:p>","DOI":"10.1145\/1455650.1455654","type":"journal-article","created":{"date-parts":[[2008,12,3]],"date-time":"2008-12-03T21:56:04Z","timestamp":1228341364000},"page":"1-20","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["Speculative return address stack management revisited"],"prefix":"10.1145","volume":"5","author":[{"given":"Hans","family":"Vandierendonck","sequence":"first","affiliation":[{"name":"Ghent University, Gent, Belgium"}]},{"given":"Andr\u00e9","family":"Seznec","sequence":"additional","affiliation":[{"name":"IRISA\/INRIA, Cedex, France"}]}],"member":"320","published-online":{"date-parts":[[2008,12]]},"reference":[{"volume-title":"Proceedings of the 2002 IEEE International Conference on Computer Design. 242--249","author":"Annavaram M.","key":"e_1_2_1_1_1","unstructured":"Annavaram , M. , Diep , T. , and Shen , J . 2002. Branch behavior of a commercial OLTP workload on intel IA32 processors . In Proceedings of the 2002 IEEE International Conference on Computer Design. 242--249 . Annavaram, M., Diep, T., and Shen, J. 2002. Branch behavior of a commercial OLTP workload on intel IA32 processors. In Proceedings of the 2002 IEEE International Conference on Computer Design. 242--249."},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859636"},{"key":"e_1_2_1_3_1","first-page":"313","article-title":"Quantifying behavioral differences between C and C++ programs","volume":"2","author":"Calder B.","year":"1994","unstructured":"Calder , B. , Grunwald , D. , and Zorn , B. 1994 . Quantifying behavioral differences between C and C++ programs . Journal of Programming Languages 2 , 4, 313 -- 351 . Calder, B., Grunwald, D., and Zorn, B. 1994. Quantifying behavioral differences between C and C++ programs. Journal of Programming Languages 2, 4, 313--351.","journal-title":"Journal of Programming Languages"},{"key":"e_1_2_1_4_1","volume-title":"Workshop on Duplicating, Deconstructing and Debunking. 25--33","author":"Desmet V.","year":"2005","unstructured":"Desmet , V. , Sazeides , Y. , Kourouyiannis , C. , and De Bosschere , K. 2005 . Correct alignment of a return-address-stack after call and return mispredictions . In Workshop on Duplicating, Deconstructing and Debunking. 25--33 . Desmet, V., Sazeides, Y., Kourouyiannis, C., and De Bosschere, K. 2005. Correct alignment of a return-address-stack after call and return mispredictions. In Workshop on Duplicating, Deconstructing and Debunking. 25--33."},{"volume-title":"Proceedings of the 30th Symposium on Microarchitecture.","author":"Driesen K.","key":"e_1_2_1_5_1","unstructured":"Driesen , K. and Holzle , U . 1998. The cascaded predictor: Economical and adaptive branch target prediction . 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In Proceedings of the 5th International Conference on Parallel Architectures and Compilation Techniques. 169--173 . Hily, S. and Seznec, A. 1996. Branch prediction and simultaneous multithreading. In Proceedings of the 5th International Conference on Parallel Architectures and Compilation Techniques. 169--173."},{"volume-title":"Proceedings of the 29th Annual ACM\/IEEE International Conference on Microarchitecture. 142--152","author":"Jacobsen E.","key":"e_1_2_1_9_1","unstructured":"Jacobsen , E. , Rotenberg , E. , and Smith , J . 1996. Assigning confidence to conditional branch predictions . In Proceedings of the 29th Annual ACM\/IEEE International Conference on Microarchitecture. 142--152 . Jacobsen, E., Rotenberg, E., and Smith, J. 1996. Assigning confidence to conditional branch predictions. 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In Proceedings of the 5th International Conference on Parallel Architectures and Compilation Techniques. 58--67."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/115952.115957"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.755465"},{"volume-title":"Proceedings of the 15th International Parallel &amp; Distributed Processing Symposium (IPDPS-01)","author":"Luo K.","key":"e_1_2_1_14_1","unstructured":"Luo , K. , Franklin , M. , Mukherjee , S. S. , and Seznec , A . 2001. Boosting SMT performance by speculation control . In Proceedings of the 15th International Parallel &amp; Distributed Processing Symposium (IPDPS-01) . Luo, K., Franklin, M., Mukherjee, S. S., and Seznec, A. 2001. Boosting SMT performance by speculation control. In Proceedings of the 15th International Parallel &amp; Distributed Processing Symposium (IPDPS-01)."},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/279358.279377"},{"volume-title":"Proceedings of the International Conference on Information Technology: Research and Education. 243--250","author":"McGregor J.","key":"e_1_2_1_16_1","unstructured":"McGregor , J. , Karig , D. , Shi , Z. , and Lee , R . 2003. A processor architecture defense against buffer overflow attacks . In Proceedings of the International Conference on Information Technology: Research and Education. 243--250 . McGregor, J., Karig, D., Shi, Z., and Lee, R. 2003. A processor architecture defense against buffer overflow attacks. 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Bulletin 30 , 11 (Apr.), 221--225. Webb, C. F. 1988. Subroutine call\/return stack. IBM Tech. Disc. Bulletin 30, 11 (Apr.), 221--225.","journal-title":"IBM Tech. Disc. Bulletin"},{"volume-title":"Proceedings of the 5th Workshop on Evaluating and Architecting System Dependability.","author":"Xu J.","key":"e_1_2_1_26_1","unstructured":"Xu , J. , Kalbarczyk , Z. , Patel , S. , and Iyer , R . 2002. Architecture support for defending against buffer overflow attacks . In Proceedings of the 5th Workshop on Evaluating and Architecting System Dependability. Xu, J., Kalbarczyk, Z., Patel, S., and Iyer, R. 2002. Architecture support for defending against buffer overflow attacks. In Proceedings of the 5th Workshop on Evaluating and Architecting System Dependability."},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/1055626.1055637"}],"container-title":["ACM Transactions on Architecture and Code Optimization"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1455650.1455654","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1455650.1455654","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T22:54:14Z","timestamp":1750287254000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1455650.1455654"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,11]]},"references-count":27,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2008,11]]}},"alternative-id":["10.1145\/1455650.1455654"],"URL":"https:\/\/doi.org\/10.1145\/1455650.1455654","relation":{},"ISSN":["1544-3566","1544-3973"],"issn-type":[{"type":"print","value":"1544-3566"},{"type":"electronic","value":"1544-3973"}],"subject":[],"published":{"date-parts":[[2008,11]]},"assertion":[{"value":"2007-10-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2008-07-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2008-12-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}