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Vector units, multiple processors\/cores, multithreading, special-purpose accelerators such as DSPs or cryptographic engines, or a combination of the above have appeared in a number of processors. They serve to address the increasing performance requirements of modern embedded applications. To what extent the available hardware parallelism can be exploited is directly dependent on the amount of parallelism inherent in the given application and the congruence between the granularity of hardware and application parallelism. This paper discusses how loop-level parallelism in embedded applications can be exploited in hardware and software. Specifically, it evaluates the efficacy of automatic loop parallelization and the performance potential of different types of parallelism, viz., true thread-level parallelism (TLP), speculative thread-level parallelism and vector parallelism, when executing loops. Additionally, it discusses the interaction between parallelization and vectorization. Applications from both the industry-standard EEMBC\u00ae,<jats:sup>1<\/jats:sup>1.1, EEMBC 2.0 and the academic MiBench embedded benchmark suites are analyzed using the Intel\u00ae<jats:sup>2<\/jats:sup>C compiler. The results show the performance that can be achieved today on real hardware and using a production compiler, provide upper bounds on the performance potential of the different types of thread-level parallelism, and point out a number of issues that need to be addressed to improve performance. The latter include parallelization of libraries such as libc and design of parallel algorithms to allow maximal exploitation of parallelism. The results also point to the need for developing new benchmark suites more suitable to parallel compilation and execution.<\/jats:p><jats:p><jats:sup>1<\/jats:sup>Other names and brands may be claimed as the property of others.<\/jats:p><jats:p><jats:sup>2<\/jats:sup>Intel is a trademark of Intel Corporation or its subsidiaries in the United States and other countries.<\/jats:p>","DOI":"10.1145\/1457255.1457257","type":"journal-article","created":{"date-parts":[[2009,2,10]],"date-time":"2009-02-10T16:42:19Z","timestamp":1234284139000},"page":"1-34","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["On the exploitation of loop-level parallelism in embedded applications"],"prefix":"10.1145","volume":"8","author":[{"given":"Arun","family":"Kejariwal","sequence":"first","affiliation":[{"name":"University of California, Irvine, CA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Alexander V.","family":"Veidenbaum","sequence":"additional","affiliation":[{"name":"University of California, Irvine, CA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Alexandru","family":"Nicolau","sequence":"additional","affiliation":[{"name":"University of California, Irvine, CA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Milind","family":"Girkar","sequence":"additional","affiliation":[{"name":"Intel Corporation"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Xinmin","family":"Tian","sequence":"additional","affiliation":[{"name":"Intel Corporation"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hideki","family":"Saito","sequence":"additional","affiliation":[{"name":"Intel Corporation"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2009,2,9]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.546611"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICPADS.2006.56"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/567067.567085"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1465482.1465560"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/268998.266637"},{"key":"e_1_2_1_6_1","unstructured":"Arm11 Family. http:\/\/www.arm.com\/products\/CPUs\/families\/ARM11Family.html. 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