{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:35:10Z","timestamp":1750307710857,"version":"3.41.0"},"reference-count":24,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2009,1,1]],"date-time":"2009-01-01T00:00:00Z","timestamp":1230768000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2009,1]]},"abstract":"<jats:p>\n            A quantum-dot cellular automata (QCA) design of an\n            <jats:italic>nxm<\/jats:italic>\n            -bit, shift-register-based memory architecture is presented. The architecture maintains data at a stable conformation, which is contrary to traditional data in-motion concept for QCA architectures. The memory architecture is based on an existing dual-phase-synchronized, line-based, one-bit QCA memory cell building block that provides size and latency improvements over other known one-bit memory cells through its novel clocking scheme. Read\/write latencies up to \u223c2X lower than the existing tile-based architecture with three-phase, line-based memory cells are obtained. Simulations with QCADesigner and HDLQ are performed on a sample 4\n            <jats:italic>x<\/jats:italic>\n            8 bit memory architecture implementation.\n          <\/jats:p>","DOI":"10.1145\/1482613.1482617","type":"journal-article","created":{"date-parts":[[2009,2,4]],"date-time":"2009-02-04T13:01:58Z","timestamp":1233752518000},"page":"1-18","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["A shift-register-based QCA memory architecture"],"prefix":"10.1145","volume":"5","author":[{"given":"Baris","family":"Taskin","sequence":"first","affiliation":[{"name":"Drexel University, Philadelphia, PA"}]},{"given":"Andy","family":"Chiu","sequence":"additional","affiliation":[{"name":"Drexel University, Philadelphia, PA"}]},{"given":"Jonathan","family":"Salkind","sequence":"additional","affiliation":[{"name":"Drexel University, Philadelphia, PA"}]},{"given":"Daniel","family":"Venutolo","sequence":"additional","affiliation":[{"name":"Drexel University, Philadelphia, PA"}]}],"member":"320","published-online":{"date-parts":[[2009,2,3]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1126\/science.284.5412.289"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775902"},{"volume-title":"Proceedings of the Great Lakes Symposium on Very Large Scale Integration (VLSI). 166--169","author":"Berzon D.","key":"e_1_2_1_3_1","unstructured":"Berzon , D. and Fountain , T. J . 1999. A memory design in QCAs using the SQUARES formalism . In Proceedings of the Great Lakes Symposium on Very Large Scale Integration (VLSI). 166--169 . Berzon, D. and Fountain, T. J. 1999. A memory design in QCAs using the SQUARES formalism. In Proceedings of the Great Lakes Symposium on Very Large Scale Integration (VLSI). 166--169."},{"key":"e_1_2_1_4_1","volume-title":"Proceedings of the Workshop on Non-Silicon Computing.","author":"Frost S.","year":"2002","unstructured":"Frost , S. , Rodrigues , A. , Janiszewski , A. , Rausch , R. , and Kogge ., P. 2002 . Memory in motion: A study of storage structures in QCA . In Proceedings of the Workshop on Non-Silicon Computing. Frost, S., Rodrigues, A., Janiszewski, A., Rausch, R., and Kogge., P. 2002. Memory in motion: A study of storage structures in QCA. In Proceedings of the Workshop on Non-Silicon Computing."},{"volume-title":"Proceedings of the IEEE Symposium on VLSI. 19--25","author":"Frost S. E.","key":"e_1_2_1_5_1","unstructured":"Frost , S. E. , Rodrigues , A. F. , Giefer , C. A. , and Kogge , P. M . 2003. Bouncing threads: Merging a new execution model into a nanotechnology memory . In Proceedings of the IEEE Symposium on VLSI. 19--25 . Frost, S. E., Rodrigues, A. F., Giefer, C. A., and Kogge, P. M. 2003. Bouncing threads: Merging a new execution model into a nanotechnology memory. In Proceedings of the IEEE Symposium on VLSI. 19--25."},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1116\/1.1394729"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2005.847034"},{"volume-title":"Proceedings of the IEEE Conference on Nanotechnology. 533--536","author":"Huang J.","key":"e_1_2_1_8_1","unstructured":"Huang , J. , Momenzadeh , M. , Schiano , L. , and Lombardi , F . 2005. Simulation-based design of modular QCA circuits . In Proceedings of the IEEE Conference on Nanotechnology. 533--536 . Huang, J., Momenzadeh, M., Schiano, L., and Lombardi, F. 2005. Simulation-based design of modular QCA circuits. In Proceedings of the IEEE Conference on Nanotechnology. 533--536."},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.1499511"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1021\/ja026856g"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2003.815857"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.124043"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2005.27"},{"key":"e_1_2_1_14_1","volume-title":"Proceedings of the IEEE Conference on Nanotechnology.","volume":"1","author":"Ottavi M.","unstructured":"Ottavi , M. , Schiano , L. , Pontarelli , S. , Vankamamidi , V. , and Lombardi , F . 2006. Timing verification of QCA memory architectures . In Proceedings of the IEEE Conference on Nanotechnology. Vol. 1 . 391--394. Ottavi, M., Schiano, L., Pontarelli, S., Vankamamidi, V., and Lombardi, F. 2006. Timing verification of QCA memory architectures. In Proceedings of the IEEE Conference on Nanotechnology. Vol. 1. 391--394."},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2005.27"},{"key":"e_1_2_1_16_1","unstructured":"Rabaey J. M. Chandrakasan A. and Nikolic B. 2003. Digital Integrated Circuits: A Design Perspective 2 ed. Prentice Hall.   Rabaey J. M. Chandrakasan A. and Nikolic B. 2003. Digital Integrated Circuits: A Design Perspective 2 ed. Prentice Hall."},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1143\/JJAP.38.7227"},{"volume-title":"Proceedings of the IEEE Conference on Nanotechnology. 302--305","author":"Taskin B.","key":"e_1_2_1_18_1","unstructured":"Taskin , B. and Hong , B . 2006. Dual-phase line-based QCA memory design . In Proceedings of the IEEE Conference on Nanotechnology. 302--305 . Taskin, B. and Hong, B. 2006. Dual-phase line-based QCA memory design. In Proceedings of the IEEE Conference on Nanotechnology. 302--305."},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2005.858589"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1057661.1057711"},{"volume-title":"Proceedings of the IEEE Conference on Nanotechnology. 343--346","author":"Vankamamidi V.","key":"e_1_2_1_21_1","unstructured":"Vankamamidi , V. , Ottavi , M. , and Lombardi , F . 2006. Clocking and cell placement for QCA . In Proceedings of the IEEE Conference on Nanotechnology. 343--346 . Vankamamidi, V., Ottavi, M., and Lombardi, F. 2006. Clocking and cell placement for QCA. In Proceedings of the IEEE Conference on Nanotechnology. 343--346."},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2003.820815"},{"key":"e_1_2_1_23_1","volume-title":"Proceedings of the Nanotechnology Conference and Trade Show.","volume":"2","author":"Walus K.","unstructured":"Walus , K. , Vetteth , A. , Julien , G. , and Dimitrov , V . 2003. Ram design using quantum-dot cellular automata . In Proceedings of the Nanotechnology Conference and Trade Show. Vol. 2 . 160--163. Walus, K., Vetteth, A., Julien, G., and Dimitrov, V. 2003. Ram design using quantum-dot cellular automata. In Proceedings of the Nanotechnology Conference and Trade Show. Vol. 2. 160--163."},{"volume-title":"Proceedings of the Device Research Conference. 121--122","author":"Yadavalli K. K.","key":"e_1_2_1_24_1","unstructured":"Yadavalli , K. K. , Orlov , A. O. , Kummamuru , R. K. , Lent , C. S. , Bernstein , G. H. , and Snider , G. L . 2005. Fanout in quantum-dot cellular automata . In Proceedings of the Device Research Conference. 121--122 . Yadavalli, K. K., Orlov, A. O., Kummamuru, R. K., Lent, C. S., Bernstein, G. H., and Snider, G. L. 2005. Fanout in quantum-dot cellular automata. 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