{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T15:57:48Z","timestamp":1761580668235,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":36,"publisher":"ACM","license":[{"start":{"date-parts":[[2009,2,22]],"date-time":"2009-02-22T00:00:00Z","timestamp":1235260800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2009,2,22]]},"DOI":"10.1145\/1508128.1508133","type":"proceedings-article","created":{"date-parts":[[2009,2,25]],"date-time":"2009-02-25T14:46:05Z","timestamp":1235573165000},"page":"23-32","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":12,"title":["Choose-your-own-adventure routing"],"prefix":"10.1145","author":[{"given":"Raphael","family":"Rubin","sequence":"first","affiliation":[{"name":"University of Pennsylvania, Philadelphia, PA, USA"}]},{"given":"Andr\u00e9","family":"DeHon","sequence":"additional","affiliation":[{"name":"University of Pennsylvania, Philadelphia, PA, USA"}]}],"member":"320","published-online":{"date-parts":[[2009,2,22]]},"reference":[{"volume-title":"http:\/\/www.itrs.net\/Links\/2005ITRS\/Home2005.htm","year":"2005","key":"e_1_3_2_1_1_1","unstructured":"International technology roadmap for semiconductors. http:\/\/www.itrs.net\/Links\/2005ITRS\/Home2005.htm , 2005 . International technology roadmap for semiconductors. http:\/\/www.itrs.net\/Links\/2005ITRS\/Home2005.htm, 2005."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/228370.228372"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2004.1274005"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.5555\/1167704.1167712"},{"key":"e_1_3_2_1_5_1","unstructured":"V. Betz. VPR and T-VPack: Versatile Packing Placement and Routing for FPGAs. http:\/\/www.eecg.toronto.edu\/~vaughn\/vpr\/vpr.html March 27 1999. Version 4.30.  V. Betz. VPR and T-VPack: Versatile Packing Placement and Routing for FPGAs. http:\/\/www.eecg.toronto.edu\/~vaughn\/vpr\/vpr.html March 27 1999. Version 4.30."},{"key":"e_1_3_2_1_6_1","unstructured":"V. Betz and J. Rose. FPGA Place-and-Route Challenge. http:\/\/www.eecg.toronto.edu\/~vaughn\/challenge\/challenge.html 1999.  V. Betz and J. Rose. FPGA Place-and-Route Challenge. http:\/\/www.eecg.toronto.edu\/~vaughn\/challenge\/challenge.html 1999."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.24"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.110"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2005.1515756"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2006.311251"},{"key":"e_1_3_2_1_11_1","first-page":"434","article-title":"Programmable logic devices with spare circuits for replacement of defects","volume":"5","author":"Cliff R. G.","year":"1995","unstructured":"R. G. Cliff , R. Raman , and S. T. Reddy . Programmable logic devices with spare circuits for replacement of defects . United States Patent Number : 5 , 434 ,514, July 18 1995 . R. G. Cliff, R. Raman, and S. T. Reddy. Programmable logic devices with spare circuits for replacement of defects. United States Patent Number: 5,434,514, July 18 1995.","journal-title":"United States Patent Number"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.5555\/549928.795751"},{"key":"e_1_3_2_1_13_1","volume-title":"Proc. MAPLD","author":"Guccione S.","year":"1999","unstructured":"S. Guccione , D. Levi , and P. Sundararajan . JBits: Java based interface for reconfigurable computing . In Proc. MAPLD , 1999 . S. Guccione, D. Levi, and P. Sundararajan. JBits: Java based interface for reconfigurable computing. In Proc. MAPLD, 1999."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2005.1568739"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/275107.275125"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/329166.329205"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/329166.329208"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1331897.1331899"},{"key":"e_1_3_2_1_19_1","first-page":"034","article-title":"Redundancy circuitry for logic circuits","volume":"6","author":"McClintock C.","year":"2000","unstructured":"C. McClintock , A. L. Lee , and R. G. Cliff . Redundancy circuitry for logic circuits . United States Patent Number : 6 , 034 ,536, March 7 2000 . C. McClintock, A. L. Lee, and R. G. Cliff. Redundancy circuitry for logic circuits. United States Patent Number: 6,034,536, March 7 2000.","journal-title":"United States Patent Number"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/201310.201328"},{"key":"e_1_3_2_1_21_1","volume-title":"The Cave of Time","author":"Packard E.","year":"1979","unstructured":"E. Packard . The Cave of Time . Bantam Books , 1979 . E. Packard. The Cave of Time. Bantam Books, 1979."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.5555\/839297.844007"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/1371579.1371582"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/1344671.1344677"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2007.70235"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/275107.275134"},{"key":"e_1_3_2_1_27_1","first-page":"251","article-title":"Structures and methods of overcoming localized defects in programmable integrated circuits by routing during the programming thereof","volume":"7","author":"Trimberger S. M.","year":"2007","unstructured":"S. M. Trimberger . Structures and methods of overcoming localized defects in programmable integrated circuits by routing during the programming thereof . United States Patent Number : 7 , 251 ,804, July 31 2007 . S. M. Trimberger. Structures and methods of overcoming localized defects in programmable integrated circuits by routing during the programming thereof. United States Patent Number: 7,251,804, July 31 2007.","journal-title":"United States Patent Number"},{"key":"e_1_3_2_1_28_1","first-page":"424","article-title":"Utilizing multiple test bitstreams to avoid localized defects in partially defective programmable integrated circuits","volume":"7","author":"Trimberger S. M.","year":"2008","unstructured":"S. M. Trimberger . Utilizing multiple test bitstreams to avoid localized defects in partially defective programmable integrated circuits . United States Patent Number : 7 , 424 ,655, September 9 2008 . S. M. Trimberger. Utilizing multiple test bitstreams to avoid localized defects in partially defective programmable integrated circuits. United States Patent Number: 7,424,655, September 9 2008.","journal-title":"United States Patent Number"},{"key":"e_1_3_2_1_29_1","first-page":"817","article-title":"Application-specific testing methods for programmable logic devices","volume":"6","author":"Wells R. W.","year":"2004","unstructured":"R. W. Wells , Z.-M. Ling , R. D. Patrie , V. L. Tong , J. Cho , and S. Toutounchi . Application-specific testing methods for programmable logic devices . United States Patent Number : 6 , 817 ,006, November 9 2004 . R. W. Wells, Z.-M. Ling, R. D. Patrie, V. L. Tong, J. Cho, and S. Toutounchi. Application-specific testing methods for programmable logic devices. United States Patent Number: 6,817,006, November 9 2004.","journal-title":"United States Patent Number"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.486270"},{"key":"e_1_3_2_1_31_1","unstructured":"Xilinx Inc. 2100 Logic Drive San Jose CA 95124. XC6200 FPGA Advanced Product Specification version 1.0 edition June 1996.  Xilinx Inc. 2100 Logic Drive San Jose CA 95124. XC6200 FPGA Advanced Product Specification version 1.0 edition June 1996."},{"key":"e_1_3_2_1_32_1","unstructured":"Xilinx Inc. 2100 Logic Drive San Jose CA 95124. Xilinx Virtex-II 1.5V Platform FPGAs Data Sheet July 2002. DS031 http:\/\/www.xilinx.com\/partinfo\/ds031.pdf.  Xilinx Inc. 2100 Logic Drive San Jose CA 95124. Xilinx Virtex-II 1.5V Platform FPGAs Data Sheet July 2002. DS031 http:\/\/www.xilinx.com\/partinfo\/ds031.pdf."},{"key":"e_1_3_2_1_33_1","unstructured":"Xilinx Inc. 2100 Logic Drive San Jose CA 95124. Xilinx Virtex-4 Family Overview June 2005. DS112 http:\/\/direct.xilinx.com\/bvdocs\/publications\/ds112.pdf.  Xilinx Inc. 2100 Logic Drive San Jose CA 95124. Xilinx Virtex-4 Family Overview June 2005. DS112 http:\/\/direct.xilinx.com\/bvdocs\/publications\/ds112.pdf."},{"key":"e_1_3_2_1_34_1","unstructured":"Xilinx Inc. 2100 Logic Drive San Jose CA 95124. Virtex FPGA Series Configuration and Readback March 2005. XAPP 138 http:\/\/www.xilinx.com\/bvdocs\/appnotes\/xapp138.pdf.  Xilinx Inc. 2100 Logic Drive San Jose CA 95124. Virtex FPGA Series Configuration and Readback March 2005. XAPP 138 http:\/\/www.xilinx.com\/bvdocs\/appnotes\/xapp138.pdf."},{"key":"e_1_3_2_1_35_1","unstructured":"Xilinx Inc. 2100 Logic Drive San Jose CA 95124. Virtex-5 FPGA Configuration User Guide September 2008. UG191 http:\/\/www.xilinx.com\/bvdocs\/userguides\/ug191.pdf.  Xilinx Inc. 2100 Logic Drive San Jose CA 95124. Virtex-5 FPGA Configuration User Guide September 2008. UG191 http:\/\/www.xilinx.com\/bvdocs\/userguides\/ug191.pdf."},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2005.1515731"}],"event":{"name":"FPGA '09: ACM\/SIGDA International Symposium on Field Programmable Gate Arrays","sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"],"location":"Monterey California USA","acronym":"FPGA '09"},"container-title":["Proceedings of the ACM\/SIGDA international symposium on Field programmable gate arrays"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1508128.1508133","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1508128.1508133","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:29:38Z","timestamp":1750253378000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1508128.1508133"}},"subtitle":["lightweight load-time defect avoidance"],"short-title":[],"issued":{"date-parts":[[2009,2,22]]},"references-count":36,"alternative-id":["10.1145\/1508128.1508133","10.1145\/1508128"],"URL":"https:\/\/doi.org\/10.1145\/1508128.1508133","relation":{},"subject":[],"published":{"date-parts":[[2009,2,22]]},"assertion":[{"value":"2009-02-22","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}