{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,10]],"date-time":"2025-12-10T08:30:38Z","timestamp":1765355438726,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":19,"publisher":"ACM","license":[{"start":{"date-parts":[[2009,2,22]],"date-time":"2009-02-22T00:00:00Z","timestamp":1235260800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2009,2,22]]},"DOI":"10.1145\/1508128.1508158","type":"proceedings-article","created":{"date-parts":[[2009,2,25]],"date-time":"2009-02-25T14:46:05Z","timestamp":1235573165000},"page":"191-200","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":96,"title":["SPR"],"prefix":"10.1145","author":[{"given":"Stephen","family":"Friedman","sequence":"first","affiliation":[{"name":"University of Washington, Seattle, WA, USA"}]},{"given":"Allan","family":"Carroll","sequence":"additional","affiliation":[{"name":"University of Washington, Seattle, WA, USA"}]},{"given":"Brian","family":"Van Essen","sequence":"additional","affiliation":[{"name":"University of Washington, Seattle, WA, USA"}]},{"given":"Benjamin","family":"Ylvisaker","sequence":"additional","affiliation":[{"name":"University of Washington, Seattle, WA, USA"}]},{"given":"Carl","family":"Ebeling","sequence":"additional","affiliation":[{"name":"University of Washington, Seattle, WA, USA"}]},{"given":"Scott","family":"Hauck","sequence":"additional","affiliation":[{"name":"University of Washington, Seattle, WA, USA"}]}],"member":"320","published-online":{"date-parts":[[2009,2,22]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Electric VLSI Design System. Sun Microsystems and Static Free Software. http:\/\/www.staticfreesoft.com\/.  Electric VLSI Design System. Sun Microsystems and Static Free Software. http:\/\/www.staticfreesoft.com\/."},{"key":"e_1_3_2_1_2_1","unstructured":"Mosaic Research Group. http:\/\/www.cs.washington.edu\/research\/lis\/mosaic\/.  Mosaic Research Group. http:\/\/www.cs.washington.edu\/research\/lis\/mosaic\/."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.5555\/647924.738755"},{"key":"e_1_3_2_1_4_1","volume-title":"Reducing the Space Complexity of Pipelined Routing Using Modified Range Encoding. In International Conference on Field-Programmable Logic and Applications","author":"Carroll A.","year":"2006","unstructured":"A. Carroll and C. Ebeling . Reducing the Space Complexity of Pipelined Routing Using Modified Range Encoding. In International Conference on Field-Programmable Logic and Applications , 2006 . A. Carroll and C. Ebeling. Reducing the Space Complexity of Pipelined Routing Using Modified Range Encoding. In International Conference on Field-Programmable Logic and Applications, 2006."},{"key":"e_1_3_2_1_5_1","volume-title":"Department of Energy NA-22 University Information Technical Interchange Review Meeting","author":"Carroll A.","year":"2007","unstructured":"A. Carroll , S. Friedman , B. Van Essen , A. Wood , B. Ylvisaker , C. Ebeling , and S. Hauck . Designing a Coarse-grained Reconfigurable Architecture for Power Efficiency. Technical report , Department of Energy NA-22 University Information Technical Interchange Review Meeting , 2007 . A. Carroll, S. Friedman, B. Van Essen, A. Wood, B. Ylvisaker, C. Ebeling, and S. Hauck. Designing a Coarse-grained Reconfigurable Architecture for Power Efficiency. Technical report, Department of Energy NA-22 University Information Technical Interchange Review Meeting, 2007."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.5555\/647923.741212"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1117201.1117227"},{"key":"e_1_3_2_1_8_1","first-page":"671","volume":"220","author":"Kirkpatrick S.","year":"1983","unstructured":"S. Kirkpatrick , C. D. Gelatt , and M. P. Vecchi . Optimization by Simulated Annealing. Science , 220 : 671 -- 680 , 1983 . S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi. Optimization by Simulated Annealing. Science, 220:671--680, 1983.","journal-title":"Optimization by Simulated Annealing. Science"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2003.1173050"},{"key":"e_1_3_2_1_10_1","first-page":"73","volume-title":"QuickRoute: A Fast Routing Algorithm for Pipelined Architectures. In IEEE International Conference on Field-Programmable Technology","author":"Li S.","year":"2004","unstructured":"S. Li and C. Ebeling . QuickRoute: A Fast Routing Algorithm for Pipelined Architectures. In IEEE International Conference on Field-Programmable Technology , pages 73 -- 80 , 2004 . S. Li and C. Ebeling. QuickRoute: A Fast Routing Algorithm for Pipelined Architectures. In IEEE International Conference on Field-Programmable Technology, pages 73--80, 2004."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/201310.201328"},{"key":"e_1_3_2_1_12_1","first-page":"166","volume-title":"DRESC: A Retargetable Compiler for Coarse-grained Reconfigurable Architectures. In IEEE International Conference on Field-Programmable Technology","author":"Mei B.","year":"2002","unstructured":"B. Mei , S. Vernalde , D. Verkest , H. De Man , and R. Lauwereins . DRESC: A Retargetable Compiler for Coarse-grained Reconfigurable Architectures. In IEEE International Conference on Field-Programmable Technology , pages 166 -- 173 , 2002 . B. Mei, S. Vernalde, D. Verkest, H. De Man, and R. Lauwereins. DRESC: A Retargetable Compiler for Coarse-grained Reconfigurable Architectures. In IEEE International Conference on Field-Programmable Technology, pages 166--173, 2002."},{"key":"e_1_3_2_1_13_1","first-page":"61","volume-title":"ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix. In International Conference on Field-Programmable Logic and Applications","volume":"2778","author":"Mei B.","year":"2003","unstructured":"B. Mei , S. Vernalde , D. Verkest , H. De Man , and R. Lauwereins . ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix. In International Conference on Field-Programmable Logic and Applications , volume 2778 , pages 61 -- 70 , 2003 . B. Mei, S. Vernalde, D. Verkest, H. De Man, and R. Lauwereins. ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix. In International Conference on Field-Programmable Logic and Applications, volume 2778, pages 61--70, 2003."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1996.564808"},{"key":"e_1_3_2_1_15_1","first-page":"323","volume-title":"Virtualization on the Tartan Reconfigurable Architecture. In International Conference on Field-Programmable Logic and Applications","author":"Mishra M.","year":"2007","unstructured":"M. Mishra and S. C. Goldstein . Virtualization on the Tartan Reconfigurable Architecture. In International Conference on Field-Programmable Logic and Applications , pages 323 -- 330 , 2007 . M. Mishra and S. C. Goldstein. Virtualization on the Tartan Reconfigurable Architecture. In International Conference on Field-Programmable Logic and Applications, pages 323--330, 2007."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/192724.192731"},{"key":"e_1_3_2_1_17_1","first-page":"427","volume-title":"Architecture-adaptive Routability-driven Placement for FPGAs. In International Conference on Field-Programmable Logic and Applications","author":"Sharma A.","year":"2005","unstructured":"A. Sharma , S. Hauck , and C. Ebeling . Architecture-adaptive Routability-driven Placement for FPGAs. In International Conference on Field-Programmable Logic and Applications , pages 427 -- 432 , 2005 . A. Sharma, S. Hauck, and C. Ebeling. Architecture-adaptive Routability-driven Placement for FPGAs. In International Conference on Field-Programmable Logic and Applications, pages 427--432, 2005."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.859540"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296442"}],"event":{"name":"FPGA '09: ACM\/SIGDA International Symposium on Field Programmable Gate Arrays","sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"],"location":"Monterey California USA","acronym":"FPGA '09"},"container-title":["Proceedings of the ACM\/SIGDA international symposium on Field programmable gate arrays"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1508128.1508158","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1508128.1508158","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:29:38Z","timestamp":1750253378000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1508128.1508158"}},"subtitle":["an architecture-adaptive CGRA mapping tool"],"short-title":[],"issued":{"date-parts":[[2009,2,22]]},"references-count":19,"alternative-id":["10.1145\/1508128.1508158","10.1145\/1508128"],"URL":"https:\/\/doi.org\/10.1145\/1508128.1508158","relation":{},"subject":[],"published":{"date-parts":[[2009,2,22]]},"assertion":[{"value":"2009-02-22","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}