{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:33:44Z","timestamp":1750307624942,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":34,"publisher":"ACM","license":[{"start":{"date-parts":[[2009,2,22]],"date-time":"2009-02-22T00:00:00Z","timestamp":1235260800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2009,2,22]]},"DOI":"10.1145\/1508128.1508207","type":"proceedings-article","created":{"date-parts":[[2009,2,25]],"date-time":"2009-02-25T14:46:05Z","timestamp":1235573165000},"page":"287-287","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["Closed-loop modeling of power and temperature profiles of FPGAs"],"prefix":"10.1145","author":[{"given":"Kanupriya","family":"Gulati","sequence":"first","affiliation":[{"name":"Texas A&M University, College Station, TX, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sunil P.","family":"Khatri","sequence":"additional","affiliation":[{"name":"Texas A&M University, College Station, TX, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Peng","family":"Li","sequence":"additional","affiliation":[{"name":"Texas A&M University, College Station, TX, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2009,2,22]]},"reference":[{"unstructured":"www.xilinx.com.  www.xilinx.com.","key":"e_1_3_2_1_1_1"},{"unstructured":"IWLS 2005 Benchmarks. http:\/\/www.iwls.org\/iwls2005\/benchmarks.html.  IWLS 2005 Benchmarks. http:\/\/www.iwls.org\/iwls2005\/benchmarks.html.","key":"e_1_3_2_1_2_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_3_1","DOI":"10.1109\/TVLS1.2004.831478"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_4_1","DOI":"10.5555\/647924.738726"},{"key":"e_1_3_2_1_5_1","first-page":"201","volume-title":"Proc. of IEEE Custom Integrated Circuit Conference","author":"Cao Y.","year":"2000","unstructured":"Y. Cao , T. Sato , D. Sylvester , M. Orshansky , and C. Hu . New paradigm of predictive MOSFET and interconnect modeling for early circuit design . In Proc. of IEEE Custom Integrated Circuit Conference , pages 201 -- 204 , Jun 2000 . http:\/\/www-device.eecs.berkeley.edu\/ ptm. Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu. New paradigm of predictive MOSFET and interconnect modeling for early circuit design. In Proc. of IEEE Custom Integrated Circuit Conference, pages 201--204, Jun 2000. http:\/\/www-device.eecs.berkeley.edu\/ ptm."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_6_1","DOI":"10.1145\/277044.277216"},{"key":"e_1_3_2_1_7_1","volume-title":"Electrothermal Analysis of VLSI Systems","author":"Cheng Y.","year":"2000","unstructured":"Y. Cheng , C. Tsai , C. Teng , and S. Kang . Electrothermal Analysis of VLSI Systems . Kluwer Academic Publishers , 2000 . Y. Cheng, C. Tsai, C. Teng, and S. Kang. Electrothermal Analysis of VLSI Systems. Kluwer Academic Publishers, 2000."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_8_1","DOI":"10.1109\/92.784093"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_9_1","DOI":"10.1145\/1120725.1120986"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_10_1","DOI":"10.1145\/996566.996572"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_11_1","DOI":"10.1145\/505388.505407"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_12_1","DOI":"10.1007\/s10470-005-6758-5"},{"key":"e_1_3_2_1_13_1","first-page":"123","volume-title":"WVLSI '01: Proceedings of the IEEE Computer Society Workshop on VLSI 2001","author":"Li H.","year":"2001","unstructured":"H. Li , W.-K. Mak , and S. Katkoori . LUT-based FPGA technology mapping for power minimization with optimal depth . In WVLSI '01: Proceedings of the IEEE Computer Society Workshop on VLSI 2001 , page 123 , Washington, DC, USA , 2001 . IEEE Computer Society. H. Li, W.-K. Mak, and S. Katkoori. LUT-based FPGA technology mapping for power minimization with optimal depth. In WVLSI '01: Proceedings of the IEEE Computer Society Workshop on VLSI 2001, page 123, Washington, DC, USA, 2001. IEEE Computer Society."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_14_1","DOI":"10.1109\/ISQED.2006.42"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_15_1","DOI":"10.1109\/ICCAD.2004.1382594"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_16_1","DOI":"10.1145\/871506.871560"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_17_1","DOI":"10.1109\/ISQED.2006.136"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_18_1","DOI":"10.1145\/968280.968293"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_19_1","DOI":"10.1109\/TCAPT.2002.808011"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_20_1","DOI":"10.1109\/CICC.2004.1358928"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_21_1","DOI":"10.1109\/MWSCAS.2002.1187013"},{"key":"e_1_3_2_1_22_1","volume-title":"Spice: A computer program to simulate computer circuits","author":"Nagel L.","year":"1995","unstructured":"L. Nagel . Spice: A computer program to simulate computer circuits . In University of California , Berkeley UCB\/ERL Memo M520, May 1995 . L. Nagel. Spice: A computer program to simulate computer circuits. In University of California, Berkeley UCB\/ERL Memo M520, May 1995."},{"key":"e_1_3_2_1_23_1","volume-title":"Digital Integrated Circuits -- a design perspective","author":"Rabaey J.","year":"1996","unstructured":"J. Rabaey . Digital Integrated Circuits -- a design perspective . Prentice Hall , 1996 . J. Rabaey. Digital Integrated Circuits -- a design perspective. Prentice Hall, 1996."},{"key":"e_1_3_2_1_24_1","first-page":"7","volume-title":"Proceedings of the Fifth Annual Austin Center for Advanced Studies Conference","author":"Rao R.","year":"2004","unstructured":"R. Rao , R. Brown , K. Nowka , and J. Burns . Analysis and mitigation of CMOS gate leakage . In Proceedings of the Fifth Annual Austin Center for Advanced Studies Conference , pages 7 -- 11 , Austin, TX , Feb 2004 . R. Rao, R. Brown, K. Nowka, and J. Burns. Analysis and mitigation of CMOS gate leakage. In Proceedings of the Fifth Annual Austin Center for Advanced Studies Conference, pages 7--11, Austin, TX, Feb 2004."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_25_1","DOI":"10.1145\/1165573.1165609"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_26_1","DOI":"10.1145\/993396.993399"},{"key":"e_1_3_2_1_27_1","volume-title":"Design Automation Conference","author":"Sangiovanni-Vincentelli A.","year":"2003","unstructured":"A. Sangiovanni-Vincentelli . The tides of EDA. Keynote Talk , Design Automation Conference , June 2003 . A. Sangiovanni-Vincentelli. The tides of EDA. Keynote Talk, Design Automation Conference, June 2003."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_28_1","DOI":"10.1145\/503048.503072"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_29_1","DOI":"10.1145\/980152.980157"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_30_1","DOI":"10.1145\/1233501.1233589"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_31_1","DOI":"10.5555\/528514"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_32_1","DOI":"10.1109\/CICC.2003.1249359"},{"key":"e_1_3_2_1_33_1","volume-title":"Principles of CMOS VLSI design -- a systems perspective","author":"Weste N.","year":"1988","unstructured":"N. Weste and K. Eshraghian . Principles of CMOS VLSI design -- a systems perspective . Addison-Wesley , 1988 . N. Weste and K. Eshraghian. Principles of CMOS VLSI design -- a systems perspective. Addison-Wesley, 1988."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_34_1","DOI":"10.1145\/605440.605447"}],"event":{"sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"],"acronym":"FPGA '09","name":"FPGA '09: ACM\/SIGDA International Symposium on Field Programmable Gate Arrays","location":"Monterey California USA"},"container-title":["Proceedings of the ACM\/SIGDA international symposium on Field programmable gate arrays"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1508128.1508207","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T12:45:53Z","timestamp":1750250753000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1508128.1508207"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,2,22]]},"references-count":34,"alternative-id":["10.1145\/1508128.1508207","10.1145\/1508128"],"URL":"https:\/\/doi.org\/10.1145\/1508128.1508207","relation":{},"subject":[],"published":{"date-parts":[[2009,2,22]]},"assertion":[{"value":"2009-02-22","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}