{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:32:13Z","timestamp":1750307533036,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":13,"publisher":"ACM","license":[{"start":{"date-parts":[[2009,5,10]],"date-time":"2009-05-10T00:00:00Z","timestamp":1241913600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2009,5,10]]},"DOI":"10.1145\/1531542.1531619","type":"proceedings-article","created":{"date-parts":[[2009,5,12]],"date-time":"2009-05-12T12:52:47Z","timestamp":1242132767000},"page":"339-344","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Accelerating multi-party scheduling for transaction-level modeling"],"prefix":"10.1145","author":[{"given":"Di","family":"Wang","sequence":"first","affiliation":[{"name":"Boston University, Boston, MA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vyas","family":"Venkataraman","sequence":"additional","affiliation":[{"name":"Boston University, Boston, MA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhen","family":"Wang","sequence":"additional","affiliation":[{"name":"Boston University, Boston, MA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wei","family":"Qin","sequence":"additional","affiliation":[{"name":"Boston University, Boston, MA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hangsheng","family":"Wang","sequence":"additional","affiliation":[{"name":"Freescale Semiconductor Inc., Austin, TX, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mrinal","family":"Bose","sequence":"additional","affiliation":[{"name":"Freescale Semiconductor Inc., Austin, TX, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jayanta","family":"Bhadra","sequence":"additional","affiliation":[{"name":"Freescale Semiconductor Inc., Austin, TX, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2009,5,10]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"IEEE Standard SystemC Language Reference Manual (1666--2005)","author":"INC.","year":"2005","unstructured":"IEEE INC. IEEE Standard SystemC Language Reference Manual (1666--2005) . New York, NY 10016--5997, USA , 2005 . IEEE INC. IEEE Standard SystemC Language Reference Manual (1666--2005). New York, NY 10016--5997, USA, 2005."},{"volume-title":"Ada Reference Manual -- Language and Standard Libraries","year":"1995","key":"e_1_3_2_1_2_1","unstructured":"ISO\/IEC(8652:1995). Ada Reference Manual -- Language and Standard Libraries . 1995 . ISO\/IEC(8652:1995). Ada Reference Manual -- Language and Standard Libraries. 1995."},{"key":"e_1_3_2_1_3_1","volume-title":"occam3 reference manual","author":"Barrett Geoff","year":"1992","unstructured":"Barrett , Geoff . occam3 reference manual . INMOS Ltd ., 1992 . Barrett, Geoff. occam3 reference manual. INMOS Ltd., 1992."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1016\/0169-7552(87)90085-7"},{"key":"e_1_3_2_1_5_1","volume-title":"Communicating Sequential Processes","author":"Hoare C.A.R.","year":"1985","unstructured":"Hoare , C.A.R. Communicating Sequential Processes . Prentice Hall , 1985 . Hoare, C.A.R. Communicating Sequential Processes. Prentice Hall, 1985."},{"key":"e_1_3_2_1_6_1","volume-title":"Communication and Concurrency","author":"Milner R.","year":"1989","unstructured":"Milner , R. Communication and Concurrency . Prentice Hall , 1989 . Milner, R. Communication and Concurrency. Prentice Hall, 1989."},{"key":"e_1_3_2_1_7_1","volume-title":"Handel-C Language Reference Manual","author":"LTD.","year":"2005","unstructured":"CELOXICA LTD. Handel-C Language Reference Manual . 2005 . CELOXICA LTD. Handel-C Language Reference Manual. 2005."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.878473"},{"key":"e_1_3_2_1_9_1","volume-title":"Haste Progamming Language Manual","author":"Handshake Solutions","year":"2008","unstructured":"Handshake Solutions , Haste Progamming Language Manual , 2008 . Handshake Solutions, Haste Progamming Language Manual, 2008."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/227595.227601"},{"key":"e_1_3_2_1_11_1","volume-title":"Bluespec: A General-Purpose Approach to High-Level Synthesis Based on Parallel Atomic Transactions","author":"Nikhil Rishiyur","year":"2008","unstructured":"Nikhil , Rishiyur . Bluespec: A General-Purpose Approach to High-Level Synthesis Based on Parallel Atomic Transactions . In Philippe Coussy, Adam Morawiec, ed., High-Level Synthesis -- From Algorithm to Digital Circuit. Springer , 2008 . Nikhil, Rishiyur. Bluespec: A General-Purpose Approach to High-Level Synthesis Based on Parallel Atomic Transactions. In Philippe Coussy, Adam Morawiec, ed., High-Level Synthesis -- From Algorithm to Digital Circuit. Springer, 2008."},{"key":"e_1_3_2_1_12_1","volume-title":"Logic-Based 0-1 Constraint Programming","author":"Barth Peter","year":"1995","unstructured":"Barth , Peter . Logic-Based 0-1 Constraint Programming . Springer , 1995 . Barth, Peter. Logic-Based 0-1 Constraint Programming. Springer, 1995."},{"key":"e_1_3_2_1_13_1","volume-title":"PCI Express System Architecture","author":"Budruk Ravi","year":"2004","unstructured":"Budruk , Ravi , Anderson , Don , and Shanley , Tom . PCI Express System Architecture . MindShare Inc , 2004 . Budruk, Ravi, Anderson, Don, and Shanley, Tom. PCI Express System Architecture. MindShare Inc, 2004."}],"event":{"name":"GLSVLSI '09: Great Lakes Symposium on VLSI 2009","sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"],"location":"Boston Area MA USA","acronym":"GLSVLSI '09"},"container-title":["Proceedings of the 19th ACM Great Lakes symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1531542.1531619","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1531542.1531619","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T12:23:13Z","timestamp":1750249393000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1531542.1531619"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,5,10]]},"references-count":13,"alternative-id":["10.1145\/1531542.1531619","10.1145\/1531542"],"URL":"https:\/\/doi.org\/10.1145\/1531542.1531619","relation":{},"subject":[],"published":{"date-parts":[[2009,5,10]]},"assertion":[{"value":"2009-05-10","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}