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In this paper, we show how hardware performance monitors can be used to provide a fine-grained, closely-coupled feedback loop to dynamic optimizations done by a multicore-aware operating system. These multicore optimizations are possible due to the advanced capabilities of hardware performance monitoring units currently found in commodity processors, such as execution pipeline stall breakdown and data address sampling. We demonstrate three case studies on how a multicore-aware operating system can use these online capabilities for (1) determining cache partition sizes, which helps reduce contention in the shared cache among applications, (2) detecting memory regions with bad cache usage, which helps in isolating these regions to reduce cache pollution, and (3) detecting sharing among threads, which helps in clustering threads to improve locality. Using realistic applications from standard benchmark suites, the following performance improvements were achieved: (1) up to 27% improvement in IPC (instructions-per-cycle) due to cache partition sizing; (2) up to 10% reduction in cache miss rates due to reduced cache pollution, resulting in up to 7% improvement in IPC; and (3) up to 70% reduction in remote cache accesses due to thread clustering, resulting in up to 7% application-level improvement.<\/jats:p>","DOI":"10.1145\/1531793.1531803","type":"journal-article","created":{"date-parts":[[2009,4,28]],"date-time":"2009-04-28T14:58:07Z","timestamp":1240930687000},"page":"56-65","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":54,"title":["Enhancing operating system support for multicore processors by using hardware performance monitoring"],"prefix":"10.1145","volume":"43","author":[{"given":"Reza","family":"Azimi","sequence":"first","affiliation":[{"name":"University of Toronto, Canada"}]},{"given":"David K.","family":"Tam","sequence":"additional","affiliation":[{"name":"University of Toronto, Canada"}]},{"given":"Livio","family":"Soares","sequence":"additional","affiliation":[{"name":"University of Toronto, Canada"}]},{"given":"Michael","family":"Stumm","sequence":"additional","affiliation":[{"name":"University of Toronto, Canada"}]}],"member":"320","published-online":{"date-parts":[[2009,4,21]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h Processors. 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