{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:53:24Z","timestamp":1750308804505,"version":"3.41.0"},"reference-count":18,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2009,6,1]],"date-time":"2009-06-01T00:00:00Z","timestamp":1243814400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2009,6]]},"abstract":"<jats:p>As one of the most promising Spintronics applications, MRAM combines the advantages of high writing and reading speed, limitless endurance, and nonvolatility. The integration of MRAM in FPGAs allows the logic circuit to rapidly configure the algorithm, the routing and logic functions, and easily realize the Runtime Reconfiguration (RTR) and multicontext configuration. However, the conventional MRAM technology based on the Field Induced Magnetic Switching (FIMS) writing approach consumes very high power, large circuit surfaces, and produces high disturbance between memory cells. These drawbacks prevent FIMS-MRAM\u2019s further development in memory and logic circuit. Thermally Assisted Switching (TAS)-based MRAM is then evaluated to address these issues. In this article, some design techniques, novel computing architecture, and logic components for FPGA logic circuits based on TAS-MRAM technology are presented. By using STMicroelectronics CMOS 90nm technology and a complete TAS-MTJ spice model, some chip characteristic results such as the programming latency (~25ns) and power dissipation (~124pJ) have been calculated or simulated to demonstrate the expected performance of TAS-MRAM-based FPGA logic circuits.<\/jats:p>","DOI":"10.1145\/1534916.1534918","type":"journal-article","created":{"date-parts":[[2009,6,16]],"date-time":"2009-06-16T12:58:25Z","timestamp":1245157105000},"page":"1-19","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":19,"title":["TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration (RTR) FPGA"],"prefix":"10.1145","volume":"2","author":[{"given":"Weisheng","family":"Zhao","sequence":"first","affiliation":[{"name":"University of Paris--Sud and CNRS"}]},{"given":"Eric","family":"Belhaire","sequence":"additional","affiliation":[{"name":"University of Paris--Sud and CNRS"}]},{"given":"Claude","family":"Chappert","sequence":"additional","affiliation":[{"name":"University of Paris--Sud and CNRS"}]},{"given":"Bernard","family":"Dieny","sequence":"additional","affiliation":[{"name":"SPINTEC"}]},{"given":"Guillaume","family":"Prenat","sequence":"additional","affiliation":[{"name":"SPINTEC"}]}],"member":"320","published-online":{"date-parts":[[2009,6]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"crossref","unstructured":"Brown S. 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G. 1999. Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems. IEEE J. Solid-State Circ. 536--548.","DOI":"10.1109\/4.753687"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.501.0081"},{"volume-title":"Spintronics: A spin-based electronics vision for the future: Magnetism and materials. Science, 1488--1495.","year":"2001","author":"Wolf S.","key":"e_1_2_1_13_1"},{"key":"e_1_2_1_14_1","unstructured":"Xilinx Corp. Virtex-4 configuration guide. http:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug071.pdf. Xilinx Corp. Virtex-4 configuration guide. http:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug071.pdf."},{"key":"e_1_2_1_15_1","doi-asserted-by":"crossref","unstructured":"Yuasa S. Nagahama T. Fukushima A. Suzuki Y. and Ando K. 2004. Giant room-temperature magnetoresistance in single-crystal Fe\/MgO\/Fe magnetic tunnel junctions. Nat. Mater. 868--871. Yuasa S. Nagahama T. Fukushima A. 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