{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,21]],"date-time":"2025-11-21T11:24:09Z","timestamp":1763724249072,"version":"3.41.0"},"reference-count":21,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2009,6,1]],"date-time":"2009-06-01T00:00:00Z","timestamp":1243814400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2009,6]]},"abstract":"<jats:p>\n            This article presents a new technology mapper, WireMap. The mapper uses an\n            <jats:italic>edge flow<\/jats:italic>\n            heuristic to improve the routability of a mapped design. The heuristic is applied during the iterative mapping optimization to reduce the total number of pin-to-pin connections (or edges). On academic benchmark (ISCAS, MCNC, and ITC designs), the average edge reduction of 9.3% is achieved while maintaining depth and LUT count compared to state-of-the-art technology mapping. Placing and routing the resulting netlists leads to an 8.5% reduction in the total wirelength, a 6.0% reduction in minimum channel width, and a 2.3% reduction in critical path delay. This technique is applied in the Xilinx ISE Design tool to evaluate its effect on industrial Virtex5 circuits. In a set of 20 large designs, we find the edge reduction is 6.8% while total wirelength measured in the placer is reduced by 3.6%. Applying WireMap has an additional advantage of reducing an average number of inputs of LUTs without increasing the total LUT count and depth. The percentages of 5- and 6-LUTs in a typical design are reduced, while the percentages of 2-, 3-, and 4-LUTs are increased. These smaller LUTs can be merged into pairs and implemented using the dual-output LUT structure found in commercial FPGAs. For academic benchmarks, WireMap leads to 9.4% fewer dual-output LUTs after merging. For the industrial designs, WireMap leads to 6.3% fewer dual-output Virtex5 LUTs.\n          <\/jats:p>","DOI":"10.1145\/1534916.1534924","type":"journal-article","created":{"date-parts":[[2009,6,16]],"date-time":"2009-06-16T12:58:25Z","timestamp":1245157105000},"page":"1-24","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":23,"title":["WireMap"],"prefix":"10.1145","volume":"2","author":[{"given":"Stephen","family":"Jang","sequence":"first","affiliation":[{"name":"Xilinx Inc."}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Billy","family":"Chan","sequence":"additional","affiliation":[{"name":"Xilinx Inc."}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kevin","family":"Chung","sequence":"additional","affiliation":[{"name":"Xilinx Inc."}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alan","family":"Mishchenko","sequence":"additional","affiliation":[{"name":"University of California, Berkeley"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2009,6]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1344671.1344675"},{"key":"e_1_2_1_2_1","unstructured":"Altera. 2008. Stratix III device handbook. http:\/\/www.altera.com\/literature\/hb\/stx3\/stratix3_handbook.pdf. Altera. 2008. Stratix III device handbook. http:\/\/www.altera.com\/literature\/hb\/stx3\/stratix3_handbook.pdf."},{"key":"e_1_2_1_3_1","unstructured":"Altera. 2004. Improving FPGA performance and area using an adaptive logic module. http:\/\/www.altera.com\/literature\/cp\/cp-01004.pdf. Altera. 2004. Improving FPGA performance and area using an adaptive logic module. http:\/\/www.altera.com\/literature\/cp\/cp-01004.pdf."},{"key":"e_1_2_1_4_1","volume-title":"ABC: A system for sequential synthesis and verification, release 61225","author":"Berkeley Logic Synthesis and Verification Group","year":"2007","unstructured":"Berkeley Logic Synthesis and Verification Group . 2007 . ABC: A system for sequential synthesis and verification, release 61225 . http:\/\/www.eecs.berkeley.edu\/~alanmi\/abc\/. Berkeley Logic Synthesis and Verification Group. 2007. ABC: A system for sequential synthesis and verification, release 61225. http:\/\/www.eecs.berkeley.edu\/~alanmi\/abc\/."},{"key":"e_1_2_1_5_1","doi-asserted-by":"crossref","unstructured":"Betz V. Rose J. and Marquardt A. 1999. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic. Betz V. Rose J. and Marquardt A. 1999. Architecture and CAD for Deep-Submicron FPGAs . Kluwer Academic.","DOI":"10.1007\/978-1-4615-5145-4"},{"volume-title":"Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD\u201905)","author":"Chatterjee S.","key":"e_1_2_1_6_1","unstructured":"Chatterjee , S. , Mishchenko , A. , Brayton , R. , Wang , X. , and Kam , T . 2005. Reducing structural bias in technology mapping . In Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD\u201905) . 519--526. Chatterjee, S., Mishchenko, A., Brayton, R., Wang, X., and Kam, T. 2005. Reducing structural bias in technology mapping. In Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD\u201905). 519--526."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382677"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.273754"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296425"},{"volume-title":"Proceedings of the Custom Integrated Circuits Conference. 85--88","author":"Gupta S.","key":"e_1_2_1_10_1","unstructured":"Gupta , S. , Anderson , A. , Farragher , L. , and Wang , Q . 2007. CAD techniques for power optimization in Virtex-5 FPGAs . In Proceedings of the Custom Integrated Circuits Conference. 85--88 . Gupta, S., Anderson, A., Farragher, L., and Wang, Q. 2007. CAD techniques for power optimization in Virtex-5 FPGAs. In Proceedings of the Custom Integrated Circuits Conference. 85--88."},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1117278.1117282"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.644605"},{"volume-title":"Proceedings of the International Workshop on Logic and Synthesis (IWLS\u201904)","author":"Manohararajah V.","key":"e_1_2_1_13_1","unstructured":"Manohararajah , V. , Brown , S. D. , and Vranesic , Z. G . 2004. Heuristics for area minimization in LUT-based FPGA technology mapping . In Proceedings of the International Workshop on Logic and Synthesis (IWLS\u201904) . 14--21. Manohararajah, V., Brown, S. D., and Vranesic, Z. G. 2004. Heuristics for area minimization in LUT-based FPGA technology mapping. In Proceedings of the International Workshop on Logic and Synthesis (IWLS\u201904). 14--21."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1117201.1117208"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147048"},{"volume-title":"Proceedings of the International Workshop on Logic and Synthesis (IWLS\u201907)","author":"Mishchenko A.","key":"e_1_2_1_16_1","unstructured":"Mishchenko , A. , Brayton , R. , Jiang , J.-H. R. , and Jang , S . 2007a. SAT-Based logic optimization and resynthesis . In Proceedings of the International Workshop on Logic and Synthesis (IWLS\u201907) . 358--364. Mishchenko, A., Brayton, R., Jiang, J.-H. R., and Jang, S. 2007a. SAT-Based logic optimization and resynthesis. In Proceedings of the International Workshop on Logic and Synthesis (IWLS\u201907). 358--364."},{"volume-title":"Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD\u201907)","author":"Mishchenko A.","key":"e_1_2_1_17_1","unstructured":"Mishchenko , A. , Cho , S. , Chatterjee , S. , and Brayton , R . 2007b. Combinational and sequential mapping with priority cuts . In Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD\u201907) . Mishchenko, A., Cho, S., Chatterjee, S., and Brayton, R. 2007b. Combinational and sequential mapping with priority cuts. In Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD\u201907)."},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/123186.123421"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/275107.275118"},{"key":"e_1_2_1_20_1","volume-title":"SIS: A system for sequential circuit synthesis. Memo. UCB\/ERL M92\/41, Department of Electrical Engineering and Computer Science","author":"Sentovich E. M.","year":"1992","unstructured":"Sentovich , E. M. , Singh , K. J. , Lavagno , L. , Moon , C. , Murgai , R. , Saldanha , A. , Savoj , H. , Stephan , P. R. , Brayton , R. , and Sangiovanni-Vincentelli , A. 1992 . SIS: A system for sequential circuit synthesis. Memo. UCB\/ERL M92\/41, Department of Electrical Engineering and Computer Science , University of California , Berkeley. May. Sentovich, E. M., Singh, K. J., Lavagno, L., Moon, C., Murgai, R., Saldanha, A., Savoj, H., Stephan, P. R., Brayton, R., and Sangiovanni-Vincentelli, A. 1992. SIS: A system for sequential circuit synthesis. Memo. UCB\/ERL M92\/41, Department of Electrical Engineering and Computer Science, University of California, Berkeley. May."},{"key":"e_1_2_1_21_1","unstructured":"Xilinx. 2006. Achieving higher system performance with the Virtex-5 family of FPGAs. http:\/\/www.xilinx.com\/support\/documentation\/white_papers\/wp245.pdf. Xilinx. 2006. Achieving higher system performance with the Virtex-5 family of FPGAs. http:\/\/www.xilinx.com\/support\/documentation\/white_papers\/wp245.pdf."}],"container-title":["ACM Transactions on Reconfigurable Technology and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1534916.1534924","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1534916.1534924","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T20:26:06Z","timestamp":1750278366000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1534916.1534924"}},"subtitle":["FPGA Technology Mapping for Improved Routability and Enhanced LUT Merging"],"short-title":[],"issued":{"date-parts":[[2009,6]]},"references-count":21,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2009,6]]}},"alternative-id":["10.1145\/1534916.1534924"],"URL":"https:\/\/doi.org\/10.1145\/1534916.1534924","relation":{},"ISSN":["1936-7406","1936-7414"],"issn-type":[{"type":"print","value":"1936-7406"},{"type":"electronic","value":"1936-7414"}],"subject":[],"published":{"date-parts":[[2009,6]]},"assertion":[{"value":"2008-05-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2008-11-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2009-06-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}