{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:35:09Z","timestamp":1750307709271,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":19,"publisher":"ACM","license":[{"start":{"date-parts":[[2009,6,8]],"date-time":"2009-06-08T00:00:00Z","timestamp":1244419200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2009,6,8]]},"DOI":"10.1145\/1542275.1542333","type":"proceedings-article","created":{"date-parts":[[2009,6,9]],"date-time":"2009-06-09T12:44:24Z","timestamp":1244551464000},"page":"410-420","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":19,"title":["Combining thread level speculation helper threads and runahead execution"],"prefix":"10.1145","author":[{"given":"Polychronis","family":"Xekalakis","sequence":"first","affiliation":[{"name":"University of Edinburgh, Edinburgh, United Kingdom"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nikolas","family":"Ioannou","sequence":"additional","affiliation":[{"name":"University of Edinburgh, Edinburgh, United Kingdom"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marcelo","family":"Cintra","sequence":"additional","affiliation":[{"name":"University of Edinburgh, Edinburgh, United Kingdom"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2009,6,8]]},"reference":[{"key":"e_1_3_2_1_1_1","first-page":"387","volume-title":"Symp. on Microarchitecture","author":"Barnes R.","year":"2003","unstructured":"R. Barnes , E. Nystrom , J. Sias , S. Patel , N. Navarro , and W. M. Hwu . '' Beating In-Order Stalls with 'Fea-Ficker' Two-Pass Pipelining.'' Intl . Symp. on Microarchitecture , pages 387 -- 398 , December 2003 . R. Barnes, E. Nystrom, J. Sias, S. Patel, N. Navarro, and W. M. Hwu. ''Beating In-Order Stalls with 'Fea-Ficker' Two-Pass Pipelining.'' Intl. Symp. on Microarchitecture, pages 387--398, December 2003."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1138035.1138038"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/300979.300995"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379248"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.43"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/263580.263597"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/291069.291020"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1007\/BF02699883"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.9"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/277830.277852"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1122971.1122997"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/305138.305214"},{"key":"e_1_3_2_1_13_1","first-page":"129","volume-title":"Symp. on High-Performance Computer Architecture","author":"Mutlu O.","year":"2003","unstructured":"O. Mutlu , J. Stark , C. Wilkerson , and Y. N. Patt . '' Runahead Execution: An Alternative to Very Large Instruction Windows.'' Intl . Symp. on High-Performance Computer Architecture , pages 129 -- 140 , February 2003 . O. Mutlu, J. Stark, C. Wilkerson, and Y. N. Patt. ''Runahead Execution: An Alternative to Very Large Instruction Windows.'' Intl. Symp. on High-Performance Computer Architecture, pages 129--140, February 2003."},{"key":"e_1_3_2_1_14_1","unstructured":"J. Renau B. Fraguela J. Tuck W. Liu M. Prvulovic L. Ceze S. Sarangi P. Sack K. Strauss and P. Montesinos. ''SESC simulator.'' http:\/\/sesc.sourceforge.net.  J. Renau B. Fraguela J. Tuck W. Liu M. Prvulovic L. Ceze S. Sarangi P. Sack K. Strauss and P. Montesinos. ''SESC simulator.'' http:\/\/sesc.sourceforge.net."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1088149.1088173"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/223982.224451"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.5555\/822079.822712"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379247"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379246"}],"event":{"name":"ICS '09: International Conference on Supercomputing","sponsor":["ACM Association for Computing Machinery","SIGARCH ACM Special Interest Group on Computer Architecture"],"location":"Yorktown Heights NY USA","acronym":"ICS '09"},"container-title":["Proceedings of the 23rd international conference on Supercomputing"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1542275.1542333","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1542275.1542333","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:30:08Z","timestamp":1750253408000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1542275.1542333"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,6,8]]},"references-count":19,"alternative-id":["10.1145\/1542275.1542333","10.1145\/1542275"],"URL":"https:\/\/doi.org\/10.1145\/1542275.1542333","relation":{},"subject":[],"published":{"date-parts":[[2009,6,8]]},"assertion":[{"value":"2009-06-08","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}