{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:35:15Z","timestamp":1750307715496,"version":"3.41.0"},"reference-count":30,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2009,7,1]],"date-time":"2009-07-01T00:00:00Z","timestamp":1246406400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","award":["2007-HJ-1602"],"award-info":[{"award-number":["2007-HJ-1602"]}],"id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2009,7]]},"abstract":"<jats:p>According to Moore's law, the number of transistors in a chip doubles every 18 months. The increased transistor-count leads to increased power density. Thus, in modern circuits, power efficiency is a central determinant of circuit efficiency. With scaling, leakage power accounts for an increasingly larger portion of the total power consumption in deep submicron technologies (&gt;40%).<\/jats:p>\n          <jats:p>FinFET technology has been proposed as a promising alternative to deep submicron bulk CMOS technology, because of its better scalability, short-channel characteristics, and ability to suppress leakage current and mitigate device-to-device variability when compared to bulk CMOS. The subthreshold slope of a FinFET is approximately 60mV which is close to ideal.<\/jats:p>\n          <jats:p>\n            In this article, we propose a methodology for low-power FinFET based circuit synthesis. A mechanism called TCMS (Threshold Control through Multiple Supply Voltages) was previously proposed for improving the power efficiency of FinFET based global interconnects. We propose a significant generalization of TCMS to the design of any logic circuit. This scheme represents a significant divergence from the conventional multiple supply voltage schemes considered in the past. It also obviates the need for voltage level-converters. We employ accurate delay and power estimates using table look-up methods based on HSPICE simulations for supply voltage and threshold voltage optimization. Experimental results demonstrate that TCMS can provide power savings of 67.6% and device area savings of 65.2% under relaxed delay constraints. Two other variants of TCMS are also proposed that yield similar benefits. We compare our scheme to extended cluster voltage scaling (ECVS), a popular dual-\n            <jats:italic>\n              V\n              <jats:sub>dd<\/jats:sub>\n            <\/jats:italic>\n            scheme presented in the literature. ECVS makes use of voltage level-converters. Even when it is assumed that these level-converters have zero delay, thus significantly favoring ECVS in time-constrained power optimization, TCMS still outperforms ECVS.\n          <\/jats:p>","DOI":"10.1145\/1543438.1543440","type":"journal-article","created":{"date-parts":[[2009,7,15]],"date-time":"2009-07-15T13:51:27Z","timestamp":1247665887000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":14,"title":["Low-power FinFET circuit synthesis using multiple supply and threshold voltages"],"prefix":"10.1145","volume":"5","author":[{"given":"Prateek","family":"Mishra","sequence":"first","affiliation":[{"name":"Princeton University, Princeton, NJ"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Anish","family":"Muttreja","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Niraj K.","family":"Jha","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2009,7,16]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1057661.1057713"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.5555\/996070.1009880"},{"volume-title":"Proceedings of the International SOI Conference. 83--84","author":"Cakici T.","key":"e_1_2_1_3_1"},{"volume-title":"Proceedings of the International Electronic Device Meeting. 719--722","author":"Chang L.","key":"e_1_2_1_4_1"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2005.856191"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1077603.1077642"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.896320"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.857149"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2007.182"},{"volume-title":"Proceedings of the International Conference Computer-Aided Design. 207--210","year":"2005","author":"King T.-J.","key":"e_1_2_1_10_1"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/16.259622"},{"volume-title":"Proceedings of the International SOI Conference. 67--68","author":"Mahmoodi H.","key":"e_1_2_1_12_1"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH.2008.4585795"},{"volume-title":"Proceedings of the International Conference on Computer Design. 560--567","author":"Muttreja A.","key":"e_1_2_1_14_1"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI.2008.117"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/MCD.2004.1263404"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1057661.1057665"},{"volume-title":"Proceedings of the International Symposium on Computer Architecture. 366--370","author":"Roy K.","key":"e_1_2_1_18_1"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1119772.1119851"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147047"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/288548.288614"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2006.10.014"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/224081.224083"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.661212"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2006.35"},{"volume-title":"Proceedings of the International SOI Conference. 82--83","author":"Wei L.","key":"e_1_2_1_26_1"},{"volume-title":"Proceedings of the International Electronic Device Meeting. 251--254","author":"Yu B.","key":"e_1_2_1_27_1"},{"key":"e_1_2_1_28_1","first-page":"2189","article-title":"Physical insights regarding design and performance of independent-gate FinFETs","volume":"52","author":"Zhang W.","year":"2005","journal-title":"IEEE Elect. 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