{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,27]],"date-time":"2026-02-27T03:46:06Z","timestamp":1772163966124,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":39,"publisher":"ACM","license":[{"start":{"date-parts":[[2009,6,20]],"date-time":"2009-06-20T00:00:00Z","timestamp":1245456000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2009,6,20]]},"DOI":"10.1145\/1555754.1555771","type":"proceedings-article","created":{"date-parts":[[2009,6,24]],"date-time":"2009-06-24T17:59:19Z","timestamp":1245866359000},"page":"116-127","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":89,"title":["Memory mapped ECC"],"prefix":"10.1145","author":[{"given":"Doe Hyun","family":"Yoon","sequence":"first","affiliation":[{"name":"University of Texas at Austin, Austin, TX, USA"}]},{"given":"Mattan","family":"Erez","sequence":"additional","affiliation":[{"name":"University of Texas at Austin, Austin, TX, USA"}]}],"member":"320","published-online":{"date-parts":[[2009,6,20]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Proceedings of IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE)","author":"Ando H.","year":"2007","unstructured":"H. Ando , K. Seki , S. Sakashita , M. Aihara , R. Kan , K. Imada , M. Itoh , M. Nagai , Y. Tosaka , K. Takahisa , and K. Hatanaka . Accelerated Testing of a 90nm SPARC64 V Microprocessor for Neutron SER . In Proceedings of IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE) , April 2007 . H. Ando, K. Seki, S. Sakashita, M. Aihara, R. Kan, K. Imada, M. Itoh, M. Nagai, Y. Tosaka, K. Takahisa, and K. Hatanaka. Accelerated Testing of a 90nm SPARC64 V Microprocessor for Neutron SER. In Proceedings of IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE), April 2007."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2006.1696325"},{"key":"e_1_3_2_1_4_1","volume-title":"Digest of Technical Papers of Symposium on VLSI Technology","author":"Chang L.","year":"2005","unstructured":"L. Chang , D. M. Fried , J. Hergenrother , J. W. Sleight , R. H. Dennard , R. K. Montoye , L. Sekaric , S. J. McNab , A. W. Topol , C. D. Adams , K. W. Guarini , and W. Haensch . Stable SRAM Cell Design for the 32nm Node and Beyond . In Digest of Technical Papers of Symposium on VLSI Technology , June 2005 . L. Chang, D. M. Fried, J. Hergenrother, J. W. Sleight, R. H. Dennard, R. K. Montoye, L. Sekaric, S. J. McNab, A. W. Topol, C. D. Adams, K. W. Guarini, and W. Haensch. Stable SRAM Cell Design for the 32nm Node and Beyond. In Digest of Technical Papers of Symposium on VLSI Technology, June 2005."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.282.0124"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.5555\/1078036.1079750"},{"key":"e_1_3_2_1_7_1","volume-title":"July","author":"Digital Equipment Corp.","year":"1999","unstructured":"Digital Equipment Corp. Alpha 21264 Microprocessor Hardware Reference Manual , July 1999 . Digital Equipment Corp. Alpha 21264 Microprocessor Hardware Reference Manual, July 1999."},{"key":"e_1_3_2_1_8_1","volume-title":"Proceedings of Workshop on Modeling, Benchmarking and Simulation","author":"Hamerly G.","year":"2005","unstructured":"G. Hamerly , E. Perelman , J. Lau , and B. Calder . SimPoint 3.0: Faster and More Flexible Program Analysis . In Proceedings of Workshop on Modeling, Benchmarking and Simulation , June 2005 . G. Hamerly, E. Perelman, J. Lau, and B. Calder. SimPoint 3.0: Faster and More Flexible Program Analysis. In Proceedings of Workshop on Modeling, Benchmarking and Simulation, June 2005."},{"key":"e_1_3_2_1_9_1","volume-title":"April","author":"Hamming R. W.","year":"1950","unstructured":"R. W. Hamming . Error Correcting and Error Detecting Codes. Bell System Technical Journal, 29:147--160 , April 1950 . R. W. Hamming. Error Correcting and Error Detecting Codes. Bell System Technical Journal, 29:147--160, April 1950."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.144.0395"},{"key":"e_1_3_2_1_11_1","volume-title":"May","author":"Huynh J.","year":"2003","unstructured":"J. Huynh . White Paper : The AMD Athlon MP Processor with 512KB L2 Cache , May 2003 . J. Huynh. White Paper: The AMD Athlon MP Processor with 512KB L2 Cache, May 2003."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2003.1196116"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.5555\/1331699.1331719"},{"key":"e_1_3_2_1_14_1","volume-title":"Proceedings of the Conference on Design Automation and Test in Europe (DATE)","author":"Kim S.","year":"2006","unstructured":"S. Kim . Area-Efficient Error Protection for Caches . In Proceedings of the Conference on Design Automation and Test in Europe (DATE) , March 2006 . S. Kim. Area-Efficient Error Protection for Caches. In Proceedings of the Conference on Design Automation and Test in Europe (DATE), March 2006."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/300979.301000"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.897148"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/360128.360132"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1013235.1013273"},{"key":"e_1_3_2_1_19_1","volume-title":"Error Control Coding: Fundamentals and Applications","author":"Lin S.","year":"1983","unstructured":"S. Lin and D. J. C. Jr . Error Control Coding: Fundamentals and Applications . Prentice-Hall, Inc. , Englewood Cliffs, NJ , 1983 . S. Lin and D. J. C. Jr. Error Control Coding: Fundamentals and Applications. Prentice-Hall, Inc., Englewood Cliffs, NJ, 1983."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065010.1065034"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.982916"},{"key":"e_1_3_2_1_22_1","volume-title":"Characterization of Multi-Bit Soft Error Events in Advanced SRAMs. In Technical Digest of IEEE International Electron Devices Meeting (IEDM)","author":"Maiz J.","year":"2003","unstructured":"J. Maiz , S. Hareland , K. Zhang , and P. Armstrong . Characterization of Multi-Bit Soft Error Events in Advanced SRAMs. In Technical Digest of IEEE International Electron Devices Meeting (IEDM) , December 2003 . J. Maiz, S. Hareland, K. Zhang, and P. Armstrong. Characterization of Multi-Bit Soft Error Events in Advanced SRAMs. In Technical Digest of IEEE International Electron Devices Meeting (IEDM), December 2003."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/1105734.1105747"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.826321"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/1479992.1480002"},{"key":"e_1_3_2_1_26_1","volume-title":"Polynomial Codes Over Certain Finite Fields","author":"Reed I. S.","year":"1960","unstructured":"I. S. Reed and G. Solomon . Polynomial Codes Over Certain Finite Fields . Journal of Society for Industrial and Applied Mathematics , 8:300--304, June 1960 . I. S. Reed and G. Solomon. Polynomial Codes Over Certain Finite Fields. Journal of Society for Industrial and Applied Mathematics, 8:300--304, June 1960."},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2006.4380862"},{"key":"e_1_3_2_1_28_1","volume-title":"Proceedings of IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE)","author":"Seifert N.","year":"2007","unstructured":"N. Seifert , V. Zia , and B. Gill . Assessing the Impact of Scaling on the Efficacy of Spatial Redundancy based Mitigation Schemes for Terrestrial Applications . In Proceedings of IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE) , April 2007 . N. Seifert, V. Zia, and B. Gill. Assessing the Impact of Scaling on the Efficacy of Spatial Redundancy based Mitigation Schemes for Terrestrial Applications. In Proceedings of IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE), April 2007."},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2005.856487"},{"key":"e_1_3_2_1_30_1","volume-title":"Performance Evaluation Corporation. SPEC CPU 2006","author":"Standard","year":"2006","unstructured":"Standard Performance Evaluation Corporation. SPEC CPU 2006 . http:\/\/www.spec.org\/cpu 2006 \/, 2006. Standard Performance Evaluation Corporation. SPEC CPU 2006. http:\/\/www.spec.org\/cpu2006\/, 2006."},{"key":"e_1_3_2_1_31_1","volume-title":"JESD89-1 System Soft Error Rate (SSER) Method and JESD89-2 Test Method for Alpha Source Accelerated Soft Error Rate","author":"Standards J.","year":"2001","unstructured":"J. Standards . JESD89 Measurement and Reporting of Alpha Particles and Terrestrial Cosmic Ray-Induced Soft Errors in Semiconductor Devices , JESD89-1 System Soft Error Rate (SSER) Method and JESD89-2 Test Method for Alpha Source Accelerated Soft Error Rate , 2001 . J. Standards. JESD89 Measurement and Reporting of Alpha Particles and Terrestrial Cosmic Ray-Induced Soft Errors in Semiconductor Devices, JESD89-1 System Soft Error Rate (SSER) Method and JESD89-2 Test Method for Alpha Source Accelerated Soft Error Rate, 2001."},{"key":"e_1_3_2_1_32_1","volume-title":"May","author":"Sun Microsystems Inc.","year":"2008","unstructured":"Sun Microsystems Inc. OpenSPARC T2 System-On-Chip (SOC) Microarchitecture Specification , May 2008 . Sun Microsystems Inc. OpenSPARC T2 System-On-Chip (SOC) Microarchitecture Specification, May 2008."},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.461.0005"},{"key":"e_1_3_2_1_34_1","volume-title":"HP Laboratories","author":"Thoziyoor S.","year":"2008","unstructured":"S. Thoziyoor , N. Muralimanohar , J. H. Ahn , and N. P. Jouppi . CACTI 5.1. Technical report , HP Laboratories , April 2008 . S. Thoziyoor, N. Muralimanohar, J. H. Ahn, and N. P. Jouppi. CACTI 5.1. Technical report, HP Laboratories, April 2008."},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/1105734.1105748"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.22"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/223982.223990"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2005.1494082"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.202"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2003.1209939"}],"event":{"name":"ISCA '09: The 36th Annual International Symposium on Computer Architecture","location":"Austin TX USA","acronym":"ISCA '09","sponsor":["ACM Association for Computing Machinery","SIGARCH ACM Special Interest Group on Computer Architecture"]},"container-title":["Proceedings of the 36th annual international symposium on Computer architecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1555754.1555771","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1555754.1555771","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T09:29:26Z","timestamp":1750238966000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1555754.1555771"}},"subtitle":["low-cost error protection for last level caches"],"short-title":[],"issued":{"date-parts":[[2009,6,20]]},"references-count":39,"alternative-id":["10.1145\/1555754.1555771","10.1145\/1555754"],"URL":"https:\/\/doi.org\/10.1145\/1555754.1555771","relation":{"is-identical-to":[{"id-type":"doi","id":"10.1145\/1555815.1555771","asserted-by":"object"}]},"subject":[],"published":{"date-parts":[[2009,6,20]]},"assertion":[{"value":"2009-06-20","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}