{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:32:07Z","timestamp":1750307527553,"version":"3.41.0"},"reference-count":28,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2009,8,1]],"date-time":"2009-08-01T00:00:00Z","timestamp":1249084800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Excellent Research Projects of National Taiwan University","award":["97R0062-05"],"award-info":[{"award-number":["97R0062-05"]}]},{"DOI":"10.13039\/501100001868","name":"National Science Council Taiwan","doi-asserted-by":"publisher","award":["NSC-97-2221-E-002-242-MY3NSC-95-2221-E-002-098-MY3NSC-96-2221-E-002-250-"],"award-info":[{"award-number":["NSC-97-2221-E-002-242-MY3NSC-95-2221-E-002-098-MY3NSC-96-2221-E-002-250-"]}],"id":[{"id":"10.13039\/501100001868","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2009,8]]},"abstract":"<jats:p>As technology continues to shrink, reducing leakage power of Field-Programmable Gate Arrays (FPGAs) becomes a critical issue for the practical use of FPGAs. In this article, we address the leakage issue of partially dynamically reconfigurable FPGA architectures with sleep transistors embedded into FPGA fabrics. In particular, we focus on eliminating leakage waste due to the delay between reconfiguration and execution time of a task. For partially dynamically reconfigurable FPGAs, the configuration prefetching technique is commonly used to hide runtime reconfiguration overhead. With prefetching, the configuration of a task is loaded into FPGAs as early as possible. Therefore, there is often a delay between reconfiguration and execution time of a task. In this period of time, the SRAM cells allocated to a task cannot be turned off even though they are not utilized.<\/jats:p>\n          <jats:p>In this article, we propose a two-stage task scheduling methodology to reduce leakage waste due to the delay between reconfiguration and execution time of a task without sacrificing performance. In the first stage, a performance-driven task scheduler that targets at minimizing the schedule length is invoked to generate an initial placement. In the second stage, a postplacement leakage-aware task scheduling is applied to refine the initial placement such that leakage waste is minimized provided that the schedule length is not increased. To solve the postplacement leakage optimization problem, we propose two algorithms. The first one is an optimal algorithm based on Integer Linear Programming (ILP). The second algorithm is a heuristic approach that iteratively refines the placement to reduce leakage waste. Experimental results on real and synthetic designs show that the efficiency and effectiveness of the proposed postplacement leakage reduction techniques.<\/jats:p>","DOI":"10.1145\/1562514.1562520","type":"journal-article","created":{"date-parts":[[2009,8,25]],"date-time":"2009-08-25T18:02:02Z","timestamp":1251223322000},"page":"1-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs"],"prefix":"10.1145","volume":"14","author":[{"given":"Ping-Hung","family":"Yuh","sequence":"first","affiliation":[{"name":"National Taiwan University, Taipei, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chia-Lin","family":"Yang","sequence":"additional","affiliation":[{"name":"National Taiwan University, Taipei, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chi-Feng","family":"Li","sequence":"additional","affiliation":[{"name":"National Taiwan University, Taipei, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chung-Hsiang","family":"Lin","sequence":"additional","affiliation":[{"name":"National Taiwan University, Taipei, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2009,8,28]]},"reference":[{"volume-title":"Stratix II Device Handbook. Altera","author":"Altera","key":"e_1_2_1_1_1","unstructured":"Altera . 2005. Stratix II Device Handbook. Altera , Inc . Altera. 2005. Stratix II Device Handbook. Altera, Inc."},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.853692"},{"key":"e_1_2_1_3_1","doi-asserted-by":"crossref","unstructured":"Banerjee S. Bozorgzadeh E. and Dutt N. 2005a. HW-SW partitioning for architectures with partial dynamic reconfiguration. Tech. rep. CECS-TR-05-02 University of California at Irvine.  Banerjee S. Bozorgzadeh E. and Dutt N. 2005a. HW-SW partitioning for architectures with partial dynamic reconfiguration. Tech. rep. CECS-TR-05-02 University of California at Irvine.","DOI":"10.1145\/1065579.1065667"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065667"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.886411"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1120725.1120985"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/871506.871535"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1090\/S0025-5718-1965-0178586-1"},{"volume-title":"Proceedings of the 6th International Workshop on Hardware\/Software Codesign (CODES), 597--601","author":"Dick R. P.","key":"e_1_2_1_9_1","unstructured":"Dick , R. P. , Rhodes , D. L. , and Wolf , W . 1998. TGFF: Task graph for free . In Proceedings of the 6th International Workshop on Hardware\/Software Codesign (CODES), 597--601 . Dick, R. P., Rhodes, D. L., and Wolf, W. 1998. TGFF: Task graph for free. In Proceedings of the 6th International Workshop on Hardware\/Software Codesign (CODES), 597--601."},{"volume-title":"Proceedings of the International Symposium on GNSS\/GPS.","author":"Engel F.","key":"e_1_2_1_10_1","unstructured":"Engel , F. , Heiser , G. , Mumford , P. , Parkinso , K. , and Rizos , C . 2004. An open gnss receiver platform architecture . In Proceedings of the International Symposium on GNSS\/GPS. Engel, F., Heiser, G., Mumford, P., Parkinso, K., and Rizos, C. 2004. An open gnss receiver platform architecture. In Proceedings of the International Symposium on GNSS\/GPS."},{"volume-title":"Proceedings of the Conference on Design, Automation and Test in Europe, 658--665","author":"Fekete S. P.","key":"e_1_2_1_11_1","unstructured":"Fekete , S. P. , K\u00f3hler , E. , and Teich , J . 2001. Optimal FPGA module placement with temporal precedence constraints . In Proceedings of the Conference on Design, Automation and Test in Europe, 658--665 . Fekete, S. P., K\u00f3hler, E., and Teich, J. 2001. Optimal FPGA module placement with temporal precedence constraints. In Proceedings of the Conference on Design, Automation and Test in Europe, 658--665."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/968280.968289"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/275107.275121"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSL.2003.821550"},{"volume-title":"Proceedings of the IEEE International Conference on Computer Design.","author":"Lach J.","key":"e_1_2_1_15_1","unstructured":"Lach , J. , Brandon , J. , and Skadron , K . 2004. A general post-processing approach to leakage current reduction in SRAM-based FPGAs . In Proceedings of the IEEE International Conference on Computer Design. Lach, J., Brandon, J., and Skadron, K. 2004. A general post-processing approach to leakage current reduction in SRAM-based FPGAs. In Proceedings of the IEEE International Conference on Computer Design."},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/611817.611844"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996767"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1046192.1046219"},{"volume-title":"Proceedings of the 8th Heterogeneous Computing Workshop (HCW), 112--124","author":"Lopez-Benitez N.","key":"e_1_2_1_19_1","unstructured":"Lopez-Benitez , N. and Hyon , J . -Y. 1999. Simulation of task graph systems in heterogeneous computing environments . In Proceedings of the 8th Heterogeneous Computing Workshop (HCW), 112--124 . Lopez-Benitez, N. and Hyon, J.-Y. 1999. Simulation of task graph systems in heterogeneous computing environments. In Proceedings of the 8th Heterogeneous Computing Workshop (HCW), 112--124."},{"key":"e_1_2_1_20_1","unstructured":"Makhorin A. GLPK (GNU linear programming kit). http:\/\/www.gnu.org\/software\/glpk\/.  Makhorin A. GLPK (GNU linear programming kit). http:\/\/www.gnu.org\/software\/glpk\/."},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147067"},{"key":"e_1_2_1_22_1","first-page":"1838","article-title":"1-V power supply high-speed digital circuit technology with multi-threahold voltage CMOS","volume":"38","author":"Mutoh S.","year":"2003","unstructured":"Mutoh , S. , Douseki , T. , Matsuya , Y. , Aoki , T. , Shigematsu , S. , and Yamada , J. 2003 . 1-V power supply high-speed digital circuit technology with multi-threahold voltage CMOS . IEEE J. Solid-State Circ. 38 , 11, 1838 -- 1845 . Mutoh, S., Douseki, T., Matsuya, Y., Aoki, T., Shigematsu, S., and Yamada, J. 2003. 1-V power supply high-speed digital circuit technology with multi-threahold voltage CMOS. IEEE J. Solid-State Circ. 38, 11, 1838--1845.","journal-title":"IEEE J. Solid-State Circ."},{"key":"e_1_2_1_23_1","unstructured":"TORSCHE. 1999. TORSCHE scheduling toolbox for matlab user's guide v0.2.0b2. In Matlab User's Guide 61.  TORSCHE. 1999. TORSCHE scheduling toolbox for matlab user's guide v0.2.0b2. In Matlab User's Guide 61."},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.818291"},{"volume-title":"Proceedings of the Custom Integrated Circuits Conference, 57--60","author":"Tuan T.","key":"e_1_2_1_25_1","unstructured":"Tuan , T. and Lai , B . 2003. Leakage power analysis of a 90nm FPGA . In Proceedings of the Custom Integrated Circuits Conference, 57--60 . Tuan, T. and Lai, B. 2003. Leakage power analysis of a 90nm FPGA. In Proceedings of the Custom Integrated Circuits Conference, 57--60."},{"volume-title":"Virtex-II Pro and Virtex II Pro X FPGA User Guide. Xilinx","author":"Xilinx","key":"e_1_2_1_26_1","unstructured":"Xilinx . 2005. Virtex-II Pro and Virtex II Pro X FPGA User Guide. Xilinx , Inc . Xilinx. 2005. Virtex-II Pro and Virtex II Pro X FPGA User Guide. Xilinx, Inc."},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382590"},{"volume-title":"Proceedings of the 9th Asia and South Pacific Design Automation Conference (ASPDAC), 725--730","author":"Yuh P.-H.","key":"e_1_2_1_28_1","unstructured":"Yuh , P.-H. , Yang , C.-L. , Chang , Y.-W. , and Chang , H . -L. 2004b. Temporal floor-planning using 3D-subTCG . In Proceedings of the 9th Asia and South Pacific Design Automation Conference (ASPDAC), 725--730 . Yuh, P.-H., Yang, C.-L., Chang, Y.-W., and Chang, H.-L. 2004b. Temporal floor-planning using 3D-subTCG. In Proceedings of the 9th Asia and South Pacific Design Automation Conference (ASPDAC), 725--730."}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1562514.1562520","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1562514.1562520","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T12:23:05Z","timestamp":1750249385000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1562514.1562520"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,8]]},"references-count":28,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2009,8]]}},"alternative-id":["10.1145\/1562514.1562520"],"URL":"https:\/\/doi.org\/10.1145\/1562514.1562520","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"type":"print","value":"1084-4309"},{"type":"electronic","value":"1557-7309"}],"subject":[],"published":{"date-parts":[[2009,8]]},"assertion":[{"value":"2008-10-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2009-05-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2009-08-28","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}