{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:32:09Z","timestamp":1750307529859,"version":"3.41.0"},"reference-count":31,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2009,9,1]],"date-time":"2009-09-01T00:00:00Z","timestamp":1251763200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2009,9]]},"abstract":"<jats:p>Coupling reconfigurable hardware accelerators with processors is an effective way to meet the performance and flexibility required to cope with modern embedded applications. The ARISE framework provides a systematic approach to extend a processor once. It will thereafter support the coupling of arbitrary hardware accelerators. The accelerators can be coupled as coprocessors or functional units of the processor\u2019s datapath, and therefore exploited as a hybrid, which includes both loose and tight computational models. This article presents a complete framework for developing applications on such hybrid reconfigurable ARISE machines. The framework integrates the automatic identification of custom instructions and the semiautomatic\/profiling-driven identification of coprocessors supporting the hybrid computational model. Moreover, it supports a modular design approach where the software and the hardware modules are developed independently and later ported into any ARISE machine with reconfigurable technology. To evaluate efficiency, a set of benchmarks is implemented on an ARISE evaluation machine utilizing the proposed framework. In addition, the ARISE machine is compared against a well-established processor paradigm that utilizes reconfigurable accelerators following only the typical coprocessor approach. Experimental results prove that the framework can be used to exploit the hybrid computational model and achieve significant performance improvements over the typical coprocessor acceleration approach. Moreover, results demonstrate how the framework can be used to trade off performance, silicon area, and application development time.<\/jats:p>","DOI":"10.1145\/1575779.1575784","type":"journal-article","created":{"date-parts":[[2009,10,6]],"date-time":"2009-10-06T18:18:59Z","timestamp":1254853139000},"page":"1-30","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["An Application Development Framework for ARISE Reconfigurable Processors"],"prefix":"10.1145","volume":"2","author":[{"given":"Nikolaos","family":"Vassiliadis","sequence":"first","affiliation":[{"name":"Aristotle University of Thessaloniki"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"George","family":"Theodoridis","sequence":"additional","affiliation":[{"name":"Aristotle University of Thessaloniki"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Spiridon","family":"Nikolaidis","sequence":"additional","affiliation":[{"name":"Aristotle University of Thessaloniki"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2009,9]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/307418.307504"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.915536"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1023\/B:IJPP.0000004508.14594.b9"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TSE.2002.1033225"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.15"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/581630.581672"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.9"},{"key":"e_1_2_1_8_1","volume-title":"<\/scp>","author":"Fritts J. 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In Proceedings of the International Symposium on Computer Architecture Power Driven Microarchitecture Workshop. 145--150 . <scp>Scott, J., Lee, L., Arends, J., and Moyer, B.<\/scp> 1998. Designing the low-power M*CORE architecture. In Proceedings of the International Symposium on Computer Architecture Power Driven Microarchitecture Workshop. 145--150."},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-005-4841-x"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.859540"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/774572.774667"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2004482"},{"volume-title":"Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS\u201907)","author":"Vassiliadis N.","key":"e_1_2_1_25_1","unstructured":"<scp> Vassiliadis , N. , Theodoridis , G. , and Nikolaidis , S . <\/scp> 2007. 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