{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:53:01Z","timestamp":1750308781081,"version":"3.41.0"},"reference-count":12,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2009,5,23]],"date-time":"2009-05-23T00:00:00Z","timestamp":1243036800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGARCH Comput. Archit. News"],"published-print":{"date-parts":[[2009,5,23]]},"abstract":"<jats:p>Many-core processor architectures require scalable solutions that reflect the locality and power constraints of future generations of silicon technology. This paper presents a many-core processor that supports an abstract model of concurrency, based on a Self-adaptive Virtual Processor (SVP). This processor implements instructions, which automatically map and schedule threads providing a code devoid of any explicit communication. The thrust of this approach is to produce binary code that is divorced from implementation parameters, yet, which still gives good performance over future generations of CMPs. A key component of this processor architecture is the memory system. This paper briefly presents the model and evaluates its memory architecture.<\/jats:p>","DOI":"10.1145\/1577129.1577136","type":"journal-article","created":{"date-parts":[[2009,7,28]],"date-time":"2009-07-28T12:43:55Z","timestamp":1248785035000},"page":"38-45","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":13,"title":["The implementation of an SVP many-core processor and the evaluation of its memory architecture"],"prefix":"10.1145","volume":"37","author":[{"given":"Chris","family":"Jesshope","sequence":"first","affiliation":[{"name":"University of Amsterdam"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mike","family":"Lankamp","sequence":"additional","affiliation":[{"name":"University of Amsterdam"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Li","family":"Zhang","sequence":"additional","affiliation":[{"name":"University of Amsterdam"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2009,7,23]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"International technology roadmap for semiconductors update. Technical report","author":"Semiconductor Industry Association","year":"2006","unstructured":"Semiconductor Industry Association ( 2006 ) International technology roadmap for semiconductors update. Technical report . Semiconductor Industry Association (2006) International technology roadmap for semiconductors update. Technical report."},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2004.91"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1007\/11859802_13"},{"key":"e_1_2_1_4_1","first-page":"127","volume-title":"International Symposium on Systems, Architectures, Modeling and Simulation, SAMOS","author":"Bernard T.A.M.","year":"2007","unstructured":"T.A.M. Bernard , C.R. Jesshope , and P.M.W. Knijnenburg ( 2007 ) Strategies for Compiling &amp;#956;TC to Novel Chip Multiprocessors , International Symposium on Systems, Architectures, Modeling and Simulation, SAMOS 2007, S. Vassiliadis et al. (Eds.), LNCS 4599 , pp. 127 -- 138 . T.A.M. Bernard, C.R. Jesshope, and P.M.W. Knijnenburg (2007) Strategies for Compiling &amp;#956;TC to Novel Chip Multiprocessors, International Symposium on Systems, Architectures, Modeling and Simulation, SAMOS 2007, S. Vassiliadis et al. (Eds.), LNCS 4599, pp. 127--138."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:19960788"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1017\/S0956796802004458"},{"key":"e_1_2_1_7_1","first-page":"1","volume-title":"Niagara 2 opens the floodgates (2006) Microprocessor Report, 20(11)","author":"McGhan H.","unstructured":"H. McGhan . Niagara 2 opens the floodgates (2006) Microprocessor Report, 20(11) , pp 1 -- 12 . H. McGhan. Niagara 2 opens the floodgates (2006) Microprocessor Report, 20(11), pp 1--12."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.5555\/1148882.1148891"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1142\/S0129626408003375"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2008.07.001"},{"key":"e_1_2_1_11_1","volume-title":"Technical report.","author":"S.R. Corporation","year":"1992","unstructured":"S.R. Corporation ( 1992 ) KSR1 technical summary , Technical report. S.R. Corporation (1992) KSR1 technical summary, Technical report."},{"key":"e_1_2_1_12_1","first-page":"38","volume-title":"Proc EuroPar 2007 Workshops. LNCS 4854","author":"Zhang L.","year":"2007","unstructured":"L. Zhang and C.R. Jesshope ( 2007 ) On-chip COMA cache-coherence protocol for microgrids of microthreaded cores. in Bouge et. al. eds ., Proc EuroPar 2007 Workshops. LNCS 4854 , Springer , pp. 38 -- 48 . L. Zhang and C.R. Jesshope (2007) On-chip COMA cache-coherence protocol for microgrids of microthreaded cores. in Bouge et. al. eds., Proc EuroPar 2007 Workshops. LNCS 4854, Springer, pp. 38--48."}],"container-title":["ACM SIGARCH Computer Architecture News"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1577129.1577136","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1577129.1577136","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T20:22:43Z","timestamp":1750278163000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1577129.1577136"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,5,23]]},"references-count":12,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2009,5,23]]}},"alternative-id":["10.1145\/1577129.1577136"],"URL":"https:\/\/doi.org\/10.1145\/1577129.1577136","relation":{},"ISSN":["0163-5964"],"issn-type":[{"type":"print","value":"0163-5964"}],"subject":[],"published":{"date-parts":[[2009,5,23]]},"assertion":[{"value":"2009-07-23","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}