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We first propose a methodology for performing an integrated optimization of both the micro-architecture and the physical circuit design of a microprocessor. In our approach, we use statistical and convex fitting methods to capture a large micro-architectural design space. We then characterize the area-delay tradeoffs of the underlying circuits through RTL synthesis. Finally, we establish the relationship between the architecture and the circuits in an integrative model, which we use to optimize the processor. As a case study, we apply this methodology to explore the performance-area tradeoffs in a highly parallel accelerator architecture for visual computing applications. Based on some early circuit tradeoff data, our results indicate that two separate designs are performance\/area optimal for our set of benchmarks: a simpler single-issue, 2-way multithreaded core running at high-frequency, and a more aggressively tuned dual-issue 4-way multithreaded design running at a lower frequency.<\/jats:p>","DOI":"10.1145\/1577129.1577138","type":"journal-article","created":{"date-parts":[[2009,7,28]],"date-time":"2009-07-28T12:43:55Z","timestamp":1248785035000},"page":"56-65","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Area-efficiency in CMP core design"],"prefix":"10.1145","volume":"37","author":[{"given":"Omid","family":"Azizi","sequence":"first","affiliation":[{"name":"Stanford University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Aqeel","family":"Mahesri","sequence":"additional","affiliation":[{"name":"University of Illinois at Urbana-Champaign"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sanjay J.","family":"Patel","sequence":"additional","affiliation":[{"name":"University of Illinois at Urbana-Champaign"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mark","family":"Horowitz","sequence":"additional","affiliation":[{"name":"Stanford University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2009,7,23]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1183401.1183430"},{"key":"e_1_2_1_2_1","volume-title":"The optimum pipeline depth for a microprocessor. isca, 00:0007","author":"Hartstein A.","year":"2002","unstructured":"A. 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The optimal logic depth per pipeline stage is 6 to 8 fo4 inverter delays. isca, 00:0014, 2002."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1105734.1105739"},{"key":"e_1_2_1_6_1","first-page":"199","volume-title":"Proceedings of the International Conference on Parallel Architectures and Compilation Techniques","author":"Huh J.","year":"2001","unstructured":"J. Huh , D. Burger , and S. Keckler . Exploring the design space of future CMPs . In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques , pages 199 -- 210 , 2001 . J. Huh, D. Burger, and S. Keckler. Exploring the design space of future CMPs. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, pages 199--210, 2001."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168882"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1152154.1152162"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.34"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346211"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2006.1598109"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1183401.1183428"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/237090.237140"},{"volume-title":"Department of Electrical Engineering","author":"Patil D.","key":"e_1_2_1_15_1","unstructured":"D. Patil , S.J. Kim , and M. Horowitz . Joint supply, threshold voltage and sizing optimization for design of robust digital circuits. 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